Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-06-18
1998-08-04
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438396, H01L 218242
Patent
active
057892890
ABSTRACT:
A unique DRAM structure has increased capacitance by using a parallel fin capacitor structure. A preferred embodiment of the invention includes a silicon substrate having a first conductivity type. Field oxide (FOX) regions are defined in the substrate to separate DRAM cells. Drain and source regions are formed in the substrate by forming in the substrate regions. On the substrate surface and between the drain and source, a gate region is formed. The gate region comprises a gate oxide, a first polysilicon layer (Poly-1) doped to have a second conductivity type opposite the first conductivity type, a tungsten silicide (WSi) layer, and an oxide layer, such as SiO.sub.2 or SiN. Oxide or TEOS (tetraethylorthosilicate) spacers cover the sides of the gate region. Above the gate region is an insulating layer of TEOS. A second polysilicon layer (Poly-2) having the second conductivity type contacts the source region and forms a bitline. Layers of WSi, oxide or thin TEOS, and Si.sub.y N.sub.x, such as Si.sub.3 N.sub.4, cover the bitline. The sides of the bitline are covered with TEOS spacers. Small TEOS regions contact portions of the drain and source regions. A capacitor having a parallel fin structure contacts the drain region. The capacitor comprises a third polysilicon layer (Poly-3) doped to the second conductivity type, a thin dielectric layer, such as a nitride film/oxide film (NO) or an oxide film
itride film/oxide film (ONO), and a fourth polysilicon layer (Poly-4) doped to the second conductivity type. Efficient methods for fabricating the DRAM are disclosed.
REFERENCES:
patent: 5185282 (1993-02-01), Lee et al.
patent: 5296400 (1994-03-01), Park et al.
patent: 5481127 (1996-01-01), Ogawa
patent: 5554557 (1996-09-01), Koh
"Silicon Processing for the VLSI Era Volume 2-Process Integration" by S. Wolf, Lattice Press, pp. 327-333, 1990.
Chang Joni Y.
Niebling John
Vanguard International Semiconductor Corporation
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