Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-06-30
2010-06-22
Brewster, William M (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S700000, C438S246000, C438S270000, C438S242000, C257S339000, C257S489000, C257S302000, C257S500000
Reexamination Certificate
active
07741178
ABSTRACT:
A method for fabricating a vertical channel transistor in a semiconductor device includes forming a plurality of pillars arranged in a first direction and a second direction crossing the first direction over a substrate, wherein each of the pillars includes a hard mask pattern thereon, forming a bit line region in the substrate between the pillars, forming a first sidewall insulation layer on a sidewall of each of the pillars, forming an insulation layer for filling a space between the pillars, forming a mask pattern for exposing the substrate between lines of the pillars arranged in the first direction over a resulting structure including the insulation layer, etching the insulation layer and the substrate using the mask pattern as an etch barrier to form a trench for defining a bit line in the substrate, and forming a second sidewall insulation layer over a resulting structure including the trench.
REFERENCES:
patent: 5541122 (1996-07-01), Tu et al.
patent: 6057243 (2000-05-01), Nagayama
patent: 6486039 (2002-11-01), Yoo et al.
patent: 6700175 (2004-03-01), Kodama et al.
patent: 7371627 (2008-05-01), Forbes
patent: 10-2005-0002424 (2005-01-01), None
patent: 10-2006-0041415 (2006-05-01), None
patent: 10-2007-0003019 (2007-01-01), None
patent: 10-2007-0056389 (2007-06-01), None
Notice of Allowance dated Aug. 31, 2009, for Korean application No. 10-2007-0136513.
Baptiste Wilner Jean
Brewster William M
Hynix / Semiconductor Inc.
Lowe Hauptman & Ham & Berner, LLP
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