Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-27
2004-06-01
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000
Reexamination Certificate
active
06743677
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the fabrication of semiconductor structures. More specifically, the present invention pertains to a method for fabricating NROM cell devices using a floating gate fabrication process.
BACKGROUND ART
Flash memory devices have found growing commercial success in the electronic device market. This is due in part to the ability of flash memory devices to store electronic data over long periods of time without an electric power supply. Additionally, flash memory devices can be erased and programmed by an end user after they are installed in an electronic device. This combined functionality is especially useful in electronic device applications where power supply is intermittent and programmability and data retention are desired such as cellular telephones, personal digital assistants, computer BIOS storage, etc.
Flash memory devices are typically configured as an array of individual memory transistors that are oriented in row and columns. This array is sometimes referred to as the core, and the memory transistors are often referred to as cells, or core cells.
FIG. 1
is a cross section view of an exemplary prior art NOR memory cell. NOR cell
100
is comprised of a substrate
101
having a source region
102
and a drain region
103
. Typically, substrate
101
is a crystalline silicon semiconductor substrate which has undergone an N-type (electron rich) doping in source area
102
and drain area
103
. In NOR cell
100
, source area
102
is comprised of a Double Diffused Implant (DDI)
105
for reducing unwanted band to band tunneling current, and a Modified Drain Diffusion implant (MDD)
106
in source area
102
and a MDD implant
107
in drain area
103
. The MDD implants provide definition of the source and drain areas (e.g., areas
102
and
103
respectively). NOR cell
100
further comprises a gate array
104
. In the embodiment of
FIG. 1
, gate array
104
is comprised of a tunnel oxide layer
108
, a floating gate
109
, an insulating layer
110
, and a control gale
111
. Typically, the substrate area underlying gate array
104
(e.g., area
104
a
of
FIG. 1
) is a lightly doped P-type (electron deficient) substrate.
Typically, the control gates (e.g., control gate
111
of
FIG. 1
) of the memory cells in each row of the core are connected to a series of word lines, thus forming individual rows of cells that can be accessed by selecting the corresponding word line. Similarly, the drain areas of the cells (e.g., drain area
103
of
FIG. 1
) in each column of the core are connected to a series of bit lines, thus forming individual columns of cells that can be accessed by selecting the corresponding bit lines. Finally, the source areas of the cells (e.g., source area
102
of
FIG. 1
) in the array are connected to a common source line. In some flash memory devices, the array of transistors is further subdivided into sectors of separate transistor arrays to provide added flexibility for the programming and erasing operations. NOR flash memory arrays are typically connected the memory cell in parallel between bit lines and ground lines. In a typical NOR flash memory array, a common source is shared between two floating gate arrays (e.g., floating gate array
104
of
FIG. 1
) and a common source is shared between two floating gate arrays. NOR flash memory arrays are used when high-speed data access a critical design factor.
The data stored in each memory cell represents a binary 1 or 0. To perform a program read or erase operation on a particular cell in the array, various predetermined voltages are applied to control gate
111
, drain area
103
and source area
102
of a memory cell. Thus, by applying these predetermined voltages to a particular bit line column, a particular word line row, and the common source line, an individual cell at the intersection of the bit line and word line (e.g., memory cell
100
) can be selected for reading or programming.
In many flash memory devices, non-volatility of the memory cells is achieved by adding a floating gate (e.g., floating gate
109
of
FIG. 1
) between the control gate
111
and the substrate region
101
of the transistors. Typically, the cells of the flash memory device are programmed by applying a predetermined raised voltage to the control gate
111
and the drain area
103
of the cell and grounding the source area
102
. As a result, the voltages on the control gate
111
and the drain area
103
cause the generation of hot electrons that are injected onto floating gate
109
, where they become trapped. This electron transfer mechanism is often referred to as Channel Hot Electron (CHE) injection. When the programming voltages are removed, the negative charge on floating gate
109
remains, thereby raising the threshold voltage of memory cell
100
. The threshold voltage is then used during reading operations to determine if memory cell
100
is in a charged or programmed state (
0
), or whether memory cell
100
is in an uncharged or erased state (
1
).
Typically, memory cells are read by applying a lower predetermined voltage to the control gate
111
and the drain area
103
and grounding the source area
102
of the memory cell. The current in the bit line is then sensed with a sense amplifier. If the cell is programmed, the threshold voltage will be relatively high and the bit line current will be zero, or at least relatively low, thus registering a binary 0. If the cell is erased, the threshold voltage will be relatively low and the bit line current will be relatively high, thus registering a binary 1.
In contrast to the programming procedure, flash memory devices can be bulk erased by simultaneously erasing all the cells in a memory sector. One procedure for erasing an entire memory sector involves applying predetermined voltages to the common source line (e.g., source area
102
of
FIG. 1
) and all the word lines (e.g., control gate
111
of
FIG. 1
) of the sector while the drain areas of the cells (e.g., drain area
103
of
FIG. 1
) are left to float. This causes electron tunneling from the floating gate
109
to the source area
102
through Fowler-Nordheim (F-N) tunneling, thereby removing the negative charge from the floating gate
109
of each of the cells in the memory sector being erased.
Fabricating semiconductor devices such as memory cell
100
involves multiple deposition, masking, etching, and doping steps in order to create the structures comprising the device. For example, referring to
FIG. 1
, cell V+ implanting is usually performed first upon substrate
101
to create a lightly doped electron deficient area (e.g., area
104
a
of
FIG. 1
) in substrate
101
. Next, a tunnel oxide layer (e.g., tunnel oxide layer
108
is then deposited and is followed by a floating gate fabrication process is performed. Typically, this requires the deposition of layer of polysilicon which is doped, either during deposition of the polysilicon layer, or in subsequently a subsequent processing step. The floating gate layer then undergoes photolithography in order to pattern floating gate
109
.
Photolithography techniques are often used in the fabrication of semiconductor structures. In one photolithography process, a pattern mask that defines the size and shape of a component in a semiconductor structure is positioned above a photosensitive layer (e.g., photoresist) that has been applied over a layer of material such as the polysilicon layer. A stepper holds the pattern mask over the photoresist and the pattern image is projected onto the photoresist through a lens. The pattern is then imprinted into the photoresist, for example, by hardening the portion of the photoresist that is exposed through the pattern mask, while the other (unexposed) portion of the photoresist remains relatively soft The softer portion of the photoresist is then removed, leaving only the harder portion on the layer. In this manner, the pattern is reproduced in the photoresist on the surface of the polysilicon layer. A portion of the polysilicon layer not underlying the photore
Hamilton Darlene G.
Le Binh Quang
Randolph Mark W.
Zheng Wei
Advanced Micro Devices , Inc.
Dang Phuc T.
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