Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-09-29
2001-07-03
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06255181
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating MOS (metal oxide semiconductor) integrated circuit devices, and more particularly to a method for forming salicide regions (self-aligned silicide regions) in a MOS transistor having an LDD (lightly doped drain) structure.
BACKGROUND OF THE INVENTION
In fabrication of MOS devices designed to have feature sizes of 0.35 &mgr;m or less, techniques for silicidation of source/drain regions and a polysilicon gate have come into wide use in MOS transistors. Of these techniques, methods for forming a self-aligned silicide region in MOS devices are disclosed in U.S. Pat. Nos. 5,567651 and 5,605,866. These silicidation methods have been employed reduce sheet resistance in an excellent ohmic contact, source/drain region, and polysilicon interconnections; to provide an increased effective contact area; and to provide an etch stopping function.
Other known methods for fabricating MOS devices having a salicide and LDD structure are disclosed in U.S. Pat. Nos. 5,089,865, 5,508,212 and 5,554,549. In these methods, alternative materials such as cobalt, platinum, palladium, nickel, molybdenum or the like are used as salicide materials. Of these salicide materials, particularly, cobalt silicide has lower resistivity in comparison to the other salicide materials, allows low temperature processing, and allows suppression of latch up at an interface of a junction region.
There is a primary known method of forming a MOS transistor having Co-silicide (cobalt silicide) and an LDD structure. In this method, a sidewall spacer formed gate structure is first formed on a semiconductor substrate, and then lightly and heavily doped impurity regions used as source/drain regions are formed by ion implantations using the gate structure as a mask. A layer of cobalt is deposited on an upper polysilicon surface of the gate structure and on an upper surface of the heavily doped impurity region using a chemical vapor deposition process.
Following the cobalt deposition, a first heat treatment, for example, a rapid thermal annealing is carried out at a low temperature in the range of 400° C. to 500° C. to form Co
2
Si and CoSi where the cobalt layer is in intimate contact with the silicon or polysilicon regions. After forming the Co
2
Si and CoSi compounds a second heat treatment is further carried out at a higher temperature to transform the Co
2
Si and CoSi compounds into CoSi
2
. CoSi
2
has a lower resistivity than Co
2
Si and CoSi formed in the initial annealing process.
However, under this process of fabricating devices void defects are thereby formed in the cobalt silicide (CoSi
2
) layer. These voids are generated having a diameter in the range of about 800 Å to 2000 Å. This leads to an increase in junction leakage current of the respective devices. As a result, the conventional MOS transistor having voids in cobalt silicide have deteriorated electrical characteristics.
The following three reasons such void defects are generated in CoSi
2
can be observed as evident by using a scanning electron microscope.
(1) An active region of a semiconductor substrate has become damaged during a dry etching process of a very thin (about 50 Å or less) gate insulating layer (for example, a gate oxide layer).
(2) The active region of the semiconductor substrate has become damaged during a dry etching process of forming a gate sidewall spacer.
(3) The active region has become damaged by injecting impurity ions directly into exposed silicon, wherein the impurity ions are accelerated with high energy.
For the above-mentioned reasons, cobalt and silicon atoms at an interface area between the cobalt and silicon layers are locally accelerated or delayed while diffusing by the heat treatment, whereby the void defects are generated.
Herein, we should give attention to the fact that damage of the active region generated due to the above reasons (1) and (2) can be sufficiently prevented by using a higher etch selectivity with respect to the gate oxide layer. The invention is thus provided to solve a problem of void defects caused by the above reason (3), that is, to prevent the active region from becoming damaged during the ion implantation for forming a heavily doped region in the active region.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method for fabricating a MOS integrated circuit device with a salicide (a self-aligned silicide region) and an LDD structure which has a small leakage function.
It is another object of the invention to provide a method for forming a LDD semiconductor device having a salicide region free from voids.
It is an additional object of the invention to provide a method for fabricating a MOS integrated circuit device which can prevent its active region from becoming damaged during ion implantation for forming a heavily doped region in the active region.
According to one aspect of the present invention, a method for fabricating a MOS transistor comprises the steps of forming a buffering layer on an active region, performing an ion injection to form a heavily doped region (source/drain region), and forming a self-aligned silicide region (salicide region) on exposed silicon and on a polysilicon gate. With the above method, when the ion injection is performed to form the source/drain region, impurity ions are injected through the buffering layer into the semiconductor substrate. As a result, the substrate surface, particularly, an upper surface of the source/drain region does not become damaged during the ion injection.
REFERENCES:
patent: 4951100 (1990-08-01), Parrillo
patent: 5428240 (1995-06-01), Lur
patent: 5554549 (1996-09-01), Huang
patent: 5858849 (1999-01-01), Chen
patent: 5891785 (1999-04-01), Chang
patent: 5923982 (1999-07-01), Kadosh et al.
patent: 5923983 (1999-07-01), Fulford, Jr. et al.
Ku Ja-Hum
Song Oh-Sung
Fourson George
Jones Volentine PLLC
Samsung Electronics Co,. Ltd.
LandOfFree
Method for fabricating MOS semiconductor device having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating MOS semiconductor device having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating MOS semiconductor device having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2525958