Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-10
2003-05-06
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S279000, C438S278000, C257S390000
Reexamination Certificate
active
06559013
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application Ser. no. 91113449, filed Jun. 20, 2002.
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a memory device. More particularly, the present invention relates to a method for fabricating a mask read-only memory (ROM) device.
2. Background of the Invention
Mask ROM device is a very basic type of read-only memory devices, in which an ion implantation process is used to adjust the threshold voltage to achieve the “on” and “off” of the memory cell. When there are changes in the product of a mask ROM device, no dramatic modification is demanded by the manufacturing process. Only one set of photoresist needs to be changed. Therefore the manufacturing of a mask ROM device is suitable for mass production. Actually, a portion of the manufacturing process can be completed first. The programming of the device can be quickly performed soon after an order is placed to move up the delivery/shipping date.
FIGS. 1A
to
1
C are schematic, cross-sectional views, illustrating the conventional fabrication process of a mask ROM device, wherein
FIGS. 1B and 1C
are views of a plane perpendicular to the plane in FIG.
1
A.
Referring to
FIG. 1A
, the conventional fabrication process of a mask ROM device includes providing a substrate
100
. A gate oxide layer
102
is then formed on the surface of the substrate
100
. An ion implantation process
106
is conducted to form a buried drain region
108
in the substrate
100
as the bit line using a patterned photoresist layer
103
as a mask.
Referring to
FIG. 1B
, after removing the patterned photoresist layer
103
, a patterned polysilicon layer
104
is formed on the gate oxide layer
102
as the word line. A patterned photoresist layer
110
is formed on the substrate
100
, exposing a channel region
114
to be coded by implantation. Further using a patterned photoresist layer
110
as a mask, a code implantation
112
is performed to implant dopants in the channel region
114
.
Thereafter, as shown in
FIG. 1C
, the photoresist layer
110
is removed to complete the programming of a mask ROM device.
However, in the mask ROM device formed by the conventional approach, the gate oxide layer formed between the substrate and the word line is very thin. The capacitance that is formed between the substrate and the word line can not be effectively reduced to properly improve the RC-delay phenomenon of the memory device. Moreover, the conventional method in programming a mask read-only memory device uses a coding mask and a high-energy ion implantation process to perform the coding implantation. When a misalignment occurs between the memory device and the coding mask, ions can not be accurately implanted to the channel region to be coded, resulting in the tail bit effect.
SUMMARY OF INVENTION
The present invention provides a method to fabricate a mask read-only memory device, wherein the tail bit effect is prevented.
The present invention also provides a fabrication method for a mask read-only memory device, wherein the RC delay phenomenon of the mask ROM device is mitigated.
The present invention provides a fabrication method for a mask ROM device, wherein a first patterned photoresist layer is formed on a substrate. An ion implantation process is conducted using the first photoresist layer as a mask to form a buried drain region in the substrate. A thick oxide layer is then formed on the surface of the substrate to cover the buried drain region subsequent to the removal of the first photoresist layer. Thereafter, a silicon nitride bar, which is perpendicular to the buried drain region is formed on the thick oxide layer. A second patterned photoresist layer is then formed on the silicon nitride bar, exposing a portion of the thick oxide layer. Using the second photoresist layer as an etching mask, the exposed portion of the thick oxide layer is removed to expose the substrate. The second photoresist layer is then removed and a thin oxide layer is formed on the exposed surface of the substrate. A polysilicon layer is then formed on the substrate. Thereafter, a portion of the polysilicon layer is removed by back-etching or chemical mechanical polishing until the silicon nitride bar is exposed for forming a plurality of coded memory cells. The coded memory cells that comprise a thick oxide layer correspond to the logic state “0”, while the memory cells that comprise a thick oxide layer correspond to the logic state “1”. A metal silicide layer is further formed on the polysilicon layer, followed by removing the silicon nitride bar to complete the programming of a mask ROM device.
The present invention provides a method for fabricating a mask ROM device. The method includes providing a substrate, wherein the substrate comprises a memory cell region and a peripheral circuit region. Moreover, an isolation structure is already formed in the peripheral circuit region to define an active region. A first patterned photoresist layer is then formed on the substrate, covering the entire peripheral circuit region and exposing the part of the substrate that is going to be formed as the buried drain region in the memory cell region. After this, a buried drain region is formed in the substrate of the memory cell region, using the first photoresist layer as an ion implantation mask. A thick oxide layer is then formed on the surface of the substrate subsequent to the removal of the first photoresist layer. A patterned silicon nitride layer is also formed on the thick oxide layer, wherein the silicon nitride layer in the memory cell region includes a plurality of bar-shaped silicon nitride layers formed perpendicular to the buried drain region, while the silicon nitride layer in the peripheral circuit region exposes the active region. A second patterned photoresist layer is then formed on the silicon nitride layer to expose a portion of the thick silicon oxide layer in the memory cell region and the peripheral circuit region. Using the second photoresist layer as an etching mask, the exposed thick silicon oxide layer in the memory cell region and the peripheral circuit region are concurrently removed to expose the substrate. The second photoresist layer is then removed and forming a gate oxide layer on the exposed substrate surface. Thereafter, a polysilicon layer is formed on the substrate. A portion of the polysilicon layer is removed by back-etching or chemical mechanical polishing until the silicon nitride layer is exposed for forming a plurality of coded memory cells in the memory cell region. The coded memory cells that comprise a gate oxide layer in the memory cell region assume a logic state of “1”, while the coded memory cells that comprise a thick oxide layer assume the logic state of “0”. A metal silicide layer is formed on the surface of the polysilicon layer. The silicon nitride layer is then removed. The polysilicon and the metal silicide structure in the memory cell region forms a word line, while the polysilicon and metal silicide structure in the peripheral circuit region serves as a gate.
According to the fabrication method of a mask ROM device of the present invention, the programming of the mask ROM device is not achieved by code implantation. The tail bit effect generated from a misalignment between the coding mask and the memory device is thus prevented.
According to the fabrication method for a mask ROM device, the memory cells that assume the logic state of “0” comprise a thick silicon oxide layer. Since the gate the thick oxide layer is thicker than the gate oxide layer, the capacitance between the word line and the substrate is lower to reduce the RC delay effect of a memory device.
Since the programming in the fabrication of a mask ROM device of the present invention is not achieved through coding implantation, the cell window of a memory device is greatly increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary,
Chen Jack
Jianq Chyun IP Office
Jr. Carl Whitehead
Macronix International Co. Ltd.
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