Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-09-25
2002-01-15
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000, C438S287000
Reexamination Certificate
active
06339000
ABSTRACT:
TECHNICAL FIELD
The present invention relates, generally, to methods for improving electrical reliability of stacked gate non-volatile memory by using an improved interpoly dielectric fabrication method using a top layer of densified silicon dioxide.
BACKGROUND ART AND TECHNICAL PROBLEMS
Modem semiconductor fabrication techniques allow Ultra Large Scale Integration (ULSI) and deep-submicron structures with feature sizes less than 0.35 micron. This, in turn, has driven the need to scale down nonvolatile memory arrays that are embedded in integrated circuit devices such as advanced microprocessors and microcontrollers. Electrically-Erasable and Programmable Read-Only Memory (EEPROM) and Flash EEPROM structures are often embedded in ICs to provide in-system reprogrammability. EEPROM is a nonvolatile form of memory which is alterable on a byte level, while flash-EEPROMs are configured to be programmed on a page or sector level.
Although a wide variety of memory cell structures are used in the semiconductor industry, a particularly desirable configuration is the stacked-gate structure. With reference to the cross-sectional representation shown in
FIG. 1
, a conventional stacked-gate memory cell
100
includes a control gate
102
, a floating gate
106
, and a channel region
114
located between a source
110
and drain
112
formed in substrate
116
Floating gate
106
is separated from channel
114
by oxide
108
, and control gate
102
is separated from floating gate
106
by dielectric
104
. Thus, the term “stacked-gate” refers to the vertically aligned nature of gate
102
, gate
106
, and channel
114
. It will be appreciated that
FIG. 1
presents a conceptual rather than a precise physical representation of a stacked-gate memory cell; certain details—side-wall dielectrics, top-side passivation, and the like—are left out for the purpose of clarity.
As gates
102
and
106
are typically fabricated from polycrystalline silicon (polysilicon, or “poly”), dielectric
104
is traditionally referred to as the “interpoly” dielectric. Moreover, due to operational details to be set forth below, oxide
108
is often referred to as the “tunnel” oxide.
Briefly, cell
100
is “discharged” by removing electrons from the floating gate
106
. Conversely, the cell is “charged” by moving electrons into the floating gate
160
(as discussed below). The presence or absence of excess negative charge consisting of electrons on floating gate
106
alters the effective threshold voltage of channel
114
(i.e., the voltage necessary to invert). Thus, given a particular control gate voltage, the channel region will or will not conduct depending on the presence of excess charge. Depending on circuit design, the charged state or the discharged state can be referred to as erased state or programmed state, respectively, or vice versa.
Those skilled in the art will realize that operation of cell
100
—particularly with respect to channel region
114
—will depend upon whether the cell utilizes an enhancement mode or depletion mode FET. Without loss of generality, however, the following discussion assumes operation in a depletion mode (i.e., n+ source and drain, p+ channel).
As mentioned briefly above, cell
100
is charged by transferring electrons to the floating gate
106
. This charge transfer to the floating gate
160
is typically accomplished through channel hot electron (CHE) injection or by Fowler Nordheim (FN) tunneling across the tunnel oxide
108
. Discharging the cell
100
by removing electrons is achieved typically from floating gate
106
, is typically achieved by FN tunneling across the tunnel oxide
108
.
Charge retention capability is critical to floating gate structures. That is, inasmuch as the primary functional of a memory cell is to store a binary value, its ability to retain a charge on the floating gate is an important indicator of reliability. Charge retention is a function of a number of factors, for example, the quality of the tunnel oxide and the materials and geometry of the interpoly dielectric. Toward this end, for reasons discussed further below, modern stacked-gate cells typically employ a three-layer interpoly structure consisting of oxide, nitride, and oxide (or oxynitride) rather than a layer (or layers) of silicon-dioxide (e.g., oxide
104
in FIG.
1
). This system is referred to as the “interpoly ONO”.
In an interpoly ONO structure (illustrated in FIG.
2
), a first layer of thermal oxide
202
is disposed by thermal oxidation of the floating gate electrode
106
. A layer of silicon nitride
204
(“nitride”) is then deposited on oxide
202
, typically using well known methods of Chemical Vapor Deposition (CVD). A layer
206
of oxide or silicon oxynitride is then formed—typically using a thermal oxidation process in steam ambience—and control gate
102
is then deposited on oxide or oxynitride
206
.
This three-level interpoly ONO structure, while superior to a single oxide level, nevertheless has some drawbacks. First, forming the top layer using prior art techniques still requires a high “thermal budget” process, i.e., steam oxidation of the nitride layer, wherein the device may reach temperatures as high as 925° C. for up to 180 minutes. This form of high-temperature processing is not suitable for sub-half-micron technology as it is known that high temperature processing steps incurred subsequent to deposition of the tunnel oxide can degrade tunnel oxide
108
material.
Background information and various details regarding ONO and tunneling oxide structures in the context of memory cells can be found in a number of documents, for example: Mori, et al.,
Polyoxide Thinning Limitation and Superior ONO Interpoly Dielectric for Nonvolatile Memory Devices,
IEEE TRANS. ON ELECT. DEV. 270, (Vol 38, No. 2, February, 1991); Mori, et al.,
High Speed Sub
-
halfmicron Flash Memory Technology with Simple Stacked Gate Structure Cell,
IEEE SYMPOSIUM ON VLSI TECHNOLOGY 53 (1994). Mori, et al.,
ONO Inter
-
Poly Dielectric Scaling for Nonvolatile Memory Applications,
IEEE TRANS. ON ELECT. DEV 386 (Vol. 38, No. 2, February 1991); and Mori, et al.,
Scaling of Tunnel Oxide Thickness for Flash EEPROMs Realizing Stress
-
Induced Leakage Current Reduction,
1994 SYMPOSIUM ON VLSI TECHNOLOGY 47 (1994).
Methods are thus needed to overcome these and other shortcomings in the prior art. Specifically, methods are needed for forming reliable, scalable, and manufacturable interpoly ONO structures which minimize tunnel oxide degradation.
SUMMARY OF THE INVENTION
The above disadvantages of the prior art may be addressed by an improved interpoly dielectric process. Methods in accordance with the present invention provide an improved interpoly dielectric structure using a densified top dielectric layer. In accordance with one aspect of the present invention, the top oxide layer of the interpoly ONO dielectric stack is formed using Low Pressure Chemical Vapor Deposition (LPCVD) of tetraethylorthosilicate (TEOS). As a result of the relatively low processing temperatures (i.e., less than about 700° C.) necessary for this step, degradation of the tunnel oxide and memory cell performance associated with high thermal-budget oxide growth processes is avoided.
In accordance with another aspect of the present invention, the top dielectric layer (e.g., TEOS) is densified using a densification process in steam ambience. This step greatly reduces erosion of the top layer TEOS during subsequent processing steps (i.e., in the context of a memory any embedded in CMOS core technology). Furthermore, this step tends to encourage formation of a thin silicon oxynitride layer at the interface of the nitride and TEOS layers, thus helping to cure “pinholes” typically associated the nitride layer and further increasing the quality and reliability of the ONO structure.
REFERENCES:
patent: 5208174 (1993-05-01), Mori
patent: 5219774 (1993-06-01), Vasche
patent: 5619052 (1997-04-01), Chang et al.
patent: 5677867 (1997-10-01), Hazani
patent: 5726087 (1998-03-01), Tseng et al.
High Temperature Oxide For NV
Bhattacharya Surya S.
Krishnamurthy Shyam
Sharma Umesh
Wu Hong J.
Bowers Charles
Chen Jack
Conexant Systems Inc.
Thomas Kayden Horstemeyer & Risley LLP
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