Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-06-13
2006-06-13
Baumeister, B. William (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S456000, C438S488000, C438S140000, C438S137000, C438S270000, C438S257000, C438S258000, C257S330000, C257S328000, C257S491000, C257S493000, C257S500000, C257S135000, C257S239000
Reexamination Certificate
active
07060562
ABSTRACT:
A method for fabricating gate electrodes (7) in a field plate trench transistor (1) having a cell array with a plurality of trenches (3) and a plurality of mesa regions (8) arranged between the trenches comprises the following steps: application of a gate electrode layer (7) to the cell array in such a way that the gate electrode layer (7) has depressions within or above the trenches (3), application of a mask layer (10) to the cell array, etching-back of the mask layer (10) in such a way that mask layer residues (10) remain only within the depressions of the gate electrode layer (7), and etching-back of the gate electrode layer (7) using the mask layer residues (10) as an etching mask in such a way that gate electrode layer residues (7) remain only within/above the trenches (3).
REFERENCES:
patent: 6924198 (2005-08-01), Williams et al.
patent: 2003/0173618 (2003-09-01), Zundel et al.
patent: 2004/0026737 (2004-02-01), Zundel et al.
patent: 2004/0031987 (2004-02-01), Henninger et al.
patent: 2004/0089910 (2004-05-01), Hirler et al.
patent: 2004/0104428 (2004-06-01), Henninger et al.
patent: 102 34 996 (2003-10-01), None
Henninger Ralf
Hiller Uli
Hirler Franz
Ropohl Jan
Baumeister B. William
Infineon - Technologies AG
Maginot Moore & Beck
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