Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-15
2002-01-08
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S588000
Reexamination Certificate
active
06337245
ABSTRACT:
This application relies for priority upon Korean Patent Application No.
99-17600,
filed on May 17, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device and a resulting semiconductor device fabricated by this method. More particularly, the present invention relates to a method for fabricating a flash memory device and a resulting flash memory device fabricated by such a method.
In contrast to a random access memory (RAM) device, a flash memory device, which is a type of a read only memory (ROM), does not lose information stored in its memory cells, even if its power supply is interrupted. Because of this characteristic, flash memory devices are being widely adopted in memory cards for computers and the like.
A unit cell of a flash memory device has the same structure as that of a memory cell of an erasable programmable ROM (EPROM) device or an electrically erasable and programmable ROM (EEPROM) device. In other words, a flash memory cell includes a tunnel oxide film, a floating gate, an inter-gate dielectric film, and a control gate electrode serving as a word line, which are sequentially stacked on a channel region.
FIG. 1
is a layout showing part of a cell array of a conventional NAND-type flash memory device. Referring to
FIG. 1
, two active regions ACT are disposed in parallel. One string selection line SSL, a plurality of word lines WL
1
, WL
2
, . . . , and WL
n
, and one ground selection line GSL are also disposed in parallel, but oriented to cross the two active regions ACT in a perpendicular direction. A contact CT exposing each active region ACT is placed on each active region ACT adjacent to the string selection line SSL.
Bit lines BL
1
and BL
2
, which are electrically connected to respective active regions ACT via each contact CT, run over each active region ACT. The active regions ACT adjacent to the ground selection line GSL are extended in a direction parallel to the ground selection line GSL so as to serve as a common source line CSL.
A floating gate isolation pattern FGI is disposed in a region between the two active regions ACT, i.e., to serve as a device isolation region. The floating gate isolation pattern FGI is disposed such that it crosses only the plurality word lines WL
1
, WL
2
, . . . , and WL
n
placed between the string selection line SSL and the ground selection line GSL.
A single memory cell, i.e., a single cell transistor, is formed at the intersection of each word line WL
1
, WL
2
, . . . , and WL
n
and each active region ACT. A gate of each cell transistor has a structure in which a tunnel oxide film, a floating gate FG (the hatched portion in FIG.
1
), an inter-gate dielectric film, and a control gate electrode corresponding to a word line are sequentially stacked on the active region ACT.
FIGS. 2A
,
3
A and
4
A are sectional views taken along the line A-A′ of
FIG. 1
, to explain a method of fabricating the conventional flash memory device.
FIGS. 2B
,
3
B and
4
B are sectional views taken along the line B-B′ of
FIG. 1
, also to explain a method for fabricating the conventional flash memory device.
Referring to
FIGS. 2A and 2B
, a device isolation film
3
is formed in a predetermined region of a semiconductor substrate
1
, using a photo mask on which the active region ACT of
FIG. 1
is engraved. A thin tunnel oxide film
5
having a thickness of
100
Å or less is formed on the surface of the active region between the device isolation films
3
. A first conductive layer, e.g., a doped polysilicon film, is formed on the entire surface of the semiconductor substrate on which the tunnel oxide film
5
has been formed. A first conductive layer pattern
7
for exposing a predetermined region of the device isolation film
3
between the adjacent active regions is formed by patterning the first conductive layer using a photo mask on which the floating gate isolation pattern FGI is engraved.
Referring to
FIGS. 3A and 3B
, an inter-gate dielectric film
9
and a second conductive layer are sequentially formed on the entire surface of the semiconductor substrate on which the first conductive pattern
7
has been formed. The second conductive layer, the inter-gate dielectric film
9
and the first conductive layer pattern
7
are consecutively patterned using a photo mask on which the plurality of word lines WL
1
, WL
2
, . . . , and WL
n
of
FIG. 1
are engraved. Accordingly, the plurality of word lines WL
1
, WL
2
, . . . , and WL
n
, which are parallel to one another, are formed and, simultaneously, the floating gate FG of
FIG. 1
is formed on the active region crossing each word line WL
1
, WL
2
, . . . , and WL
n
.
At this time, the inter-gate dielectric film
9
remaining at the sidewalls of the first conductive layer pattern
7
between the plurality of word lines WL
1
, WL
2
, . . . , and WL
n
should be completely removed. If a part of the inner-gate dielectric film
9
remains on the sidewalls of the first conductive layer pattern
7
between the plurality of word lines WL
1
, WL
2
, . . . , and WL
n
, the first conductive layer pattern
7
between the plurality of word lines WL
1
, WL
2
, . . . , and WL
n
is also not completely removed, thereby forming a stringer of the first conductive material. The stringer can electrically connect adjacent floating gates FG to each other. This can cause a problem in which an unselected second cell is also programmed when a selected first cell is being programmed.
As a result of this, the inter-gate dielectric film
9
, which is exposed after the second conductive layer is etched, should be over etched. This results in a recess of the device isolation film
3
exposed between the plurality word lines WL
1
, WL
2
, . . . , and WL
n
, as shown in
FIG. 3B
, thereby reducing the thickness of the device isolation film
3
. Of course, the recess phenomenon in the device isolation film
3
becomes more serious as the first conductive layer pattern
7
becomes thicker, requiring greater etching to remove.
Referring to
FIGS. 4A and 4B
, impurities of a different conductivity type to that of the semiconductor substrate
1
are implanted into the active region exposed between the plurality of word lines WL
1
, WL
2
, . . . , and WL
n
, thereby forming source and drain regions SD
1
and SD
2
, respectively, for each cell transistor. At this time, as shown in
FIGS. 4A and 4B
, the impurities may also be implanted into the semiconductor substrate
1
under the recessed device isolation film
3
, thereby forming a field inversion layer FI. Accordingly, an electrical isolation characteristic between adjacent source and drain regions SD
1
and SD
2
is reduced so that a leakage current I
b
may flow when different voltages are applied to the source and drain regions SD
1
and SD
2
. Consequently, when selectively programming one cell of the flash memory device fabricated according to the conventional technology described above, it is possible that an unselected memory cell may also be programmed.
With reference to
FIGS. 1
,
4
A, and
4
B, general conditions required for programming a selected memory cell S will now be described. Primarily, the voltage of 0V is applied to a selected bit line connected to a string including the selected memory cell S, e.g., the first bit line BL
1
, and a program inhibition voltage VP
pi
that is close to a power supply voltage V
cc
is applied to the unselected bit lines, e.g., the second bit line BL
2
. A program voltage V
p
of about 15V is applied to a selected word line that serves as a control gate electrode of the selected memory cell S, e.g., the second word line WL
2
. A pass voltage V
pass
of about 8V is then applied to unselected word lines WL
1
, . . . , and WL
n
other than the selected word line (WL
2
in this example) and the string selection line SSL. The voltage of 0V is applied to the ground selection line GSL, the common source line CSL, and the semiconductor substrate
1
.
As describe above
Chaudhari Chandra
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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