Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent
1996-04-09
2001-01-02
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000
Utility Patent
active
06168987
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a dynamic random access memory (DRAM) and, more particularly, to an efficient method for fabricating crown-shaped capacitor structures for DRAMs using self aligned spacers.
2. Discussion of Related Art
A DRAM memory typically comprises a transistor and a capacitor. Binary information (e.g., a 0 or 1) is stored in the capacitor in the form of an electric charge. Capacitors do not store electric charges perfectly and lose their charge if not refreshed on a regular basis, such as every 2 ms. The capacitors, however, allow information (in the form of electrical charges) to be quickly stored and accessed.
FIG. 1
illustrates a typical DRAM cell
100
. The DRAM cell
100
of
FIG. 1
comprises a metal oxide semiconductor field effect transistor (MOSFET)
102
, and a capacitor
104
. A word line is connected to the gate G of the MOSFET
102
. A bitline is connected to the source S of the MOSFET
102
. The capacitor
104
is connected to the drain D of the MOSFET.
The state of the DRAM cell
100
is determined by whether or not the capacitor
104
is holding a charge. The DRAM cell is addressed (i.e., activated) by the word line. When the DRAM cell is activated, it may be read or written into. The DRAM cell
100
is read by using the bitline to determine whether a voltage appears at the source S, indicating the presence or absence of a charge stored in the capacitor
104
. The DRAM cell is written into by using the bitline to add or remove charge from the capacitor
104
.
As DRAM technology advances, the chip area used for one DRAM cell is becoming smaller. This permits more DRAM cells per unit area, resulting in a memory array storing more information in the same area than was possible in previous memory arrays. As the chip area decreases, however, it becomes increasingly difficult to fabricate a capacitor having sufficient capacitance to store a charge for a sufficient time.
Two methods may be used to increase the capacitance of a DRAM cell capacitor. One method is to decrease the effective dielectric thickness of the capacitor; the other method is to increase the effective capacitor surface area. It is expected that future DRAM cells will rely heavily on the quality and storage capacity of ultra thin dielectric materials that are sandwiched between two heavily doped polysilicon and/or silicon electrodes. However, higher capacitance values cannot be obtained by using very thin dielectric material without seriously degrading the device retention time (that is, the time between refreshes). This is because films thinner than 50 Ångstroms present excessive leakage current due to direct carrier tunneling. Therefore, in order to design smaller DRAM cells, it is desirable to increase the surface area of the DRAM cell capacitor to result in a capacitance capable of storing a charge for a sufficient time. Designing such a DRAM cell is challenging because of the conflicting design characteristics: the overall cell size is preferably minimized while the capacitor surface area is preferably maximized.
FIG. 2
illustrates a prior art DRAM cell
200
described in U.S. Pat. No. 5,185,282 issued to Lee et al. The DRAM cell
200
comprises a MOSFET
202
and a capacitor
204
, both formed on a silicon substrate
206
having a first conductivity type (i.e., p-type). The MOSFET
202
comprises the source
208
and drain
210
regions, which regions are separated by a channel
212
. The source and drain regions
208
,
210
have a conductivity type opposite to that of the substrate
206
(i.e., n-type). A polysilicide bitline
214
directly contacts the source region
208
. A bitline oxide layer
216
and a nitride layer
218
are disposed on top of the bitline
214
. The bitline oxide layer includes spacers
216
A,
216
B which cover the sides of the bitline.
A gate
220
is formed from a first layer of conducting polysilicon material (Poly-1) and is separated from the surface of the substrate
206
by a gate oxide layer
222
. An oxide layer
224
is on top of the gate
220
. Oxide spacers
224
A,
224
B cover the sides of the gate. Field oxide regions
226
are located in the substrate
206
and separate adjacent DRAM cells.
The capacitor
204
sits on top of the drain region
210
. The capacitor
204
has a first electrode
230
formed by a conducting polysilicon material (Poly-2), a thin dielectric layer
232
which may be, for example, silicon nitride film/oxide film (NO) or oxide film/silicon nitride film/oxide film (ONO), and a second electrode
234
which is formed from a layer of conducting polysilicon material (Poly-3). The capacitor contacts the drain region
210
in a space called the contact hole
236
. The capacitors form a crown-shaped region over the DRAM cell.
The DRAM cell of
FIG. 2
is fabricated by the following process:
1. Deposit a pad oxide film and silicon nitride film on the substrate
206
. These films are masked, and the unmasked portions are etched away to expose areas of the substrate. Boron is implanted on the substrate and the substrate is re-oxidized to create field oxide (FOX) regions
222
. The pad oxide and silicon nitride films are removed.
2. The gate oxide
222
and Poly-1
220
are deposited. The Poly-1 layer is doped to a particular conductivity, and the oxide layer
224
is deposited over the doped Poly-1. These layers are masked and etched to form the gate region. The oxide layer is re-grown and anisotropically etched using the reactive ion etching (RIE) method to form spacers
224
A,
224
B on the side of the Poly-1 layer.
3. The exposed portion of the substrate
206
(i.e., the portion not below the gate) is ion implanted to create the source and drain regions
208
,
210
. A polysilicon layer is deposited, doped, and processed to become polysilicide. This layer is subsequently used to form the polysilicide bitline
214
. The bitline oxide layer
216
is deposited over the polysilicide layer. These layers are masked and etched to define the bitline
214
contacting the source region
208
. The bitline oxide layer
216
is re-grown and anisotropically etched using the RIE method to form spacers on the sides of the bitline
214
. The nitride blanket
218
is then deposited over the entire cell. The nitride blanket
218
is used as an etch-stop for the next step.
4. The nitride blanket is masked and etched to leave nitride over the bitline
214
and part of the gate region. An oxide film is deposited over the cell. This oxide film is patterned using photolithographic techniques and etched to form an oxide grid in which the contact hole
236
is formed. The oxide grid is patterned using lift off or multi-layer resist, over exposure, or advanced lithographic technique. This grid also defines the crown shape that the capacitor will take when formed.
5. A layer of polysilicon (Poly-2) is deposited over the entire grid to create the first capacitor electrode
230
. The spaces defined by the grid are filled with photoresist and the top portion of the Poly-2 layer is etched back to isolate adjacent capacitors from one another. The oxide film is etched away, and the capacitor electrode is doped to a particular conductivity. The capacitor dielectric
232
is deposited over the doped capacitor electrode
230
and a third polysilicon layer (Poly-3) is deposited over the dielectric
232
to form the second capacitor electrode
234
.
In this way, a DRAM having a crown-shaped capacitor is fabricated.
It is an object of the present invention to provide a DRAM having a crown-shaped capacitor fabrication method that is more efficient than the prior art methods.
It is another object of the present invention to provide a DRAM having a crown-shaped capacitor that does not have a nitride layer over the bitline.
SUMMARY OF THE INVENTION
These and other objects of the present invention are achieved by a unique and efficient method for fabricating a DRAM having a crown-shaped capacitor structure. The DRAM has a crown-shaped capacitor structure and is formed on a subs
Chien Rong-Wu
Jeng Erik S.
Liaw Ing-Ruey
Nath & Associates
Novick Harold L.
Tsai Jey
Vanguard International Semiconductor Corp.
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