Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-02-11
2000-10-24
Nelms, David
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438254, 438258, 438259, 438262, 438267, 438275, 438299, 438396, 438397, H01L 218242
Patent
active
061366439
ABSTRACT:
A method for making capacitor-over-bit line (COB) DRAM using a self-aligned contact etching technology is achieved. After forming FET gate electrodes, sidewall spacers are formed from a first Si.sub.3 N.sub.4 etch-stop layer, while a portion of the Si.sub.3 N.sub.4 is retained as an etch-stop layer on the source/drain areas. Self-aligned contact openings are etched in a first oxide layer to the source/drain areas, and polysilicon landing plugs are formed in all the self-aligned openings. A second oxide layer is deposited and contact holes are etched to the landing plugs for bit lines. A polycide layer having a cap layer is deposited and patterned to form bit lines. A third Si.sub.3 N.sub.4 etch-stop layer is conformally deposited over the bit lines and patterned to form openings over the landing plugs for the capacitor node contacts while forming Si.sub.3 N.sub.4 sidewall spacers on the bit lines exposed in the openings. A third oxide layer is deposited, and openings having relaxed alignment tolerances, can be etched to the capacitor node contacts because the underlying third etch-stop layer prevents overetching. A conducting layer is deposited and etched back to form bottom electrodes in the openings, and the third oxide layer is removed, while the Si.sub.3 N.sub.4 etch-stop layers prevents over-etching. An interelectrode dielectric layer is deposited, and capacitor top electrodes are formed.
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Chen Chun-Yao
Jeng Erik S.
Liaw Ing-Ruey
Sung Janmye
Ackerman Stephen B.
Hoang Quoc
Nelms David
Saile George O.
Vanguard International Semiconductor Company
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