Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-07-24
1999-06-29
Chang, Joni Y.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438254, H01L 218242
Patent
active
059181206
ABSTRACT:
A method and structure are described for making DRAM devices having bit line contacts for memory cells and landing plugs for peripheral devices with a Ti/TiN barrier layer patterned to form bit lines and local interconnections. FETs are formed on the substrate for memory cells and for devices in the peripheral area. A planar first insulating layer is deposited, and contact openings are formed to the devices. A Ti/TiN barrier layer is deposited in the contact openings and a tungsten (W) layer is deposited and selectively etched back to the barrier layer. The barrier layer is then patterned to form bit lines and local interconnections. A second insulating layer is deposited, and capacitor node contact openings are etched and filled with polysilicon to form node contacts on which capacitors are fabricated. A planar third insulating layer is formed and multilevel contact openings are etched to landing plugs. Metal plugs are formed in the multilevel contact openings, and a first metal is deposited and patterned to form the first level of metal interconnections. The reduced height of the Ti/TiN bit lines and the landing plug contacts significantly reduce the aspect ratio of the multilevel contacts, allowing for fabricating DRAM circuits with higher density and improved reliability.
REFERENCES:
patent: 5130885 (1992-07-01), Fazan et al.
patent: 5364817 (1994-11-01), Lur et al.
patent: 5534462 (1996-07-01), Fiordalice et al.
patent: 5576240 (1996-11-01), Radosevich et al.
patent: 5631179 (1997-05-01), Sung et al.
patent: 5780338 (1998-07-01), Jeng et al.
patent: 5837591 (1998-11-01), Shimada et al.
Ackerman Stephen B.
Chang Joni Y.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Method for fabricating capacitor-over-bit line (COB) dynamic ran does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating capacitor-over-bit line (COB) dynamic ran, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating capacitor-over-bit line (COB) dynamic ran will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1386401