Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-30
2001-03-27
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S202000, C438S227000, C438S298000
Reexamination Certificate
active
06207484
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and a semiconductor device fabricated by the method, and more particularly, to a method for fabricating a BiCDMOS device where a bipolar junction transistor, a complementary metal-oxide-semiconductor (CMOS) electric field effect transistor and a double diffused metal-oxide-semiconductor (DMOS) electric field effect transistor are formed on a single wafer, and to a BiCDMOS device fabricated by the method.
2. Description of the Related Art
BiCDMOS technology includes bipolar technology, CMOS technology and DMOS technology. That is, BiCDMOS technology can attain low power consumption, a small noise margin and a high integration density for CMOS technology, high switching speed and input and output speed for bipolar technology, and high power characteristics for DMOS technology. Thus, a power device and a logic device can be integrated onto a single chip, thereby reducing the chip size, reducing power consumption and withstanding high voltage and drive at high current. However, the technology of fabricating a BiCDMOS device is very complicated and requires many mask layers, thereby increasing manufacturing cost. Thus, a method for fabricating a BiCDMOS device reducing the number of required mask layers to lower the unit cost and increase performance of the device is required.
Meanwhile, a DMOS device included in the BiCDMOS device exhibit problems such as turn-on phenomenon of a parasitic transistor, and device failure due to excessive reverse-directional current.
FIG. 1
is a sectional view showing an example of a horizontal DMOS transistor included in a conventional BiCDMOS device, showing two cells in common using a source electrode.
Referring to
FIG. 1
, an n-type highly-doped buried layer
11
is formed on a semiconductor substrate
10
doped with p-type impurities, and an n-type lightly-doped epitaxial layer
12
is formed on the n
+
-type buried layer
11
. An n-type lightly-doped well region
13
is formed on the n-type epitaxial layer
12
, and a p-type base region
14
is formed on the n-type well region
13
. Also, n-type base regions
15
a
and
15
b
are formed at the sides of the p-type base region
14
, spaced apart by a predetermined distance. N-type highly-doped source regions
16
a
and
16
b
are formed in the p-type base region
14
. Meanwhile, n-type highly-doped drain regions
17
a
and
17
b
are formed on the n-type base regions
15
a
and
15
b
, respectively.
A source electrode
18
is formed to electrically contact the n-type source regions
16
a
and
16
b
and the p-type base region
14
. Gate electrodes
19
a
and
19
b
are formed at the sides of the source electrode
18
, spaced apart from the source electrode
18
by a predetermined distance. The gate electrodes
19
a
and
19
b
are formed on an oxide layer
20
at the sides of the n-type source regions
16
a
and
16
b
and over the p-type base region
14
. Also, drain electrodes
21
a
and
21
b
electrically contact the n-type drain regions
17
a
and
17
b
. Meanwhile, the source electrode
18
, the gate electrodes
19
a
and
19
b
and the drain electrodes
21
a
and
21
b
are insulated by an insulating layer
22
.
In the horizontal DMOS transistor, a parasitic npn bipolar transistor composed of the n-type source regions
16
a
and
16
b
, the p-type base region
14
and the n-type drain regions
17
a
and
17
b
is turned on by voltage drop due to a current flowing through resistance R
b
of the p-type base region
14
. Consequently, the gate electrodes
19
a
and
19
b
cannot be controlled, and as such, a device can be damaged. The current flowing through the resistance R
b
of the p-type base region
14
includes first zener diode current I
z1
. Here, the first zener diode current I
z1
means current flowing through a first zener diode component
24
a
when overcurrent flows due to the inductance component of a load during the turn-off of a device to apply a voltage more than a predetermined voltage (zener voltage) between the p-type base region
14
and the drain regions
17
a
and
17
b.
A deep p+ region
23
is formed deeply in the p-type base region
14
. The deep p+ region
23
reduces resistance R
b
of the p-type base region
14
. In addition, a second zener diode current I
z2
flowing through a second zener diode component
24
b
is formed between the deep p+ region
23
and the n-type buried layer
11
, thereby reducing the amount of first zener diode current I
z1
that passes through the resistance R
b
of the p-type base region
14
.
However, an additional mask layer is required for forming the deep p+ region
23
, which complicates the fabrication process. Also, in a low pressure process, even though the concentration of the p+ region
23
is increased, the zener voltage of the first zener diode component
24
a
may be lower than the zener voltage of the second zener diode component
24
b.
Thus, even though the resistance R
b
of the p-type base region
14
is reduced, the first zener diode current I
z1
flows through the resistance R
b
pf the p-type base region
14
, such that the parasitic npn bipolar transistor can be easily turned on. As a result, the reliability of the device can be deteriorated.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a method for fabricating a BiCDMOS device capable of reducing the number of used mask layers to lower the cost and increase performance.
It is another objective of the present invention to provide a BiCDMOS device fabricated by the above method.
Accordingly, to achieve the first objective, in a method for fabricating a BiCDMOS device according to the present invention, a semiconductor region of a second conductivity type is formed on a semiconductor substrate of a first conductivity type. Well regions of the first conductivity type and well regions of the second conductivity type are formed in a selected region of the semiconductor region. An oxidation passivation layer pattern defining a region where a pad oxide layer and a field oxide layer are to be formed is formed on a surface of the substrate where the well regions are formed. Impurity ions of the first conductivity type are implanted into the entire surface of a region where a field oxide layer is to be formed, using the oxidation passivation layer pattern as an ion implantation mask. An ion implantation mask pattern defining a field region of the second conductivity type is formed on a substrate where the oxidation passivation layer pattern is formed. Impurity ions of the second conductivity type are implanted using the ion implantation mask pattern. The ion implantation mask pattern is removed. A field oxide layer is formed by annealing with respect to the substrate where the oxidation passivation layer pattern is formed. And at the same time, a field region of the first conductivity type and a field region of the second conductivity type are formed.
Preferably, the method further comprises the step of forming buried layers of the first conductivity type and the second conductivity type in the selected region of the semiconductor substrate, before step of forming the well regions of first and second conductivity types. Here, the step of forming the buried layers of the first and the second conductivity types comprises the substeps of: forming buried layers of the second conductivity type in the predetermined region of the semiconductor substrate; implanting impurities of the first conductivity type into a region except the region where the buried layers of the second conductivity type are formed, and into part of a region of the buried layers of the second conductivity type formed in region corresponding to a region where the double diffused MOS transistor is to be formed; and diffusing impurities of the first conductivity type to form buried layers of the first conductivity type, where the buried layer of the first conductivity type formed in the region corresponding to the
Choi Yong-Cheol
Kim Chul-Joong
Kim Jong-Hwan
Lee Suk-Kyun
Marger & Johnson & McCollom, P.C.
Pham Long
Samsung Electronics Co,. Ltd.
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