Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-12-06
2000-03-07
Fahmy, Wael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438234, 438416, 438420, 257370, H01L 218238
Patent
active
060339462
ABSTRACT:
A method for making an isolated NMOS transistor (10) in a BiCMOS process includes forming an N- conductivity type DUF layer (19) in a P conductivity type semiconductor substrate (12), followed by forming alternate contiguous N+ and P conductivity type buried regions (30,26) in the substrate (12). A layer of substantially intrinsic semiconductor material (32) is then formed on the substrate (12) in which alternate and contiguous N and P conductivity type wells (35,36) are formed, respectively above and extending to the N+ and P conductivity type buried regions (30,26). Finally, NMOS source and drain regions (48) are formed in at least one of the P conductivity type wells (35). The method is preferably performed concurrently with the construction of a bipolar transistor structure (11) elsewhere on the substrate (12). More particularly, the steps of forming the P conductivity type buried layer (30) may be performed a part of a simultaneous formation of a collector element of the PNP transistor (11) elsewhere on the substrate (12).
REFERENCES:
patent: 4855244 (1989-08-01), Hutter et al.
patent: 5171699 (1992-12-01), Hutter et al.
patent: 5348907 (1994-09-01), Migita
patent: 5702959 (1997-12-01), Hutter et al.
Hutter Louis N.
Smith Jeffrey P.
Brady III Wade James
Donaldson Richard L.
Fahmy Wael
Pham Long
Texas Instruments Incorporated
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