Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-07
2001-07-10
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S129000, C438S612000, C438S666000
Reexamination Certificate
active
06258706
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a chess-board patterned bond pad structure that has stress buffered characteristics and a method for making such structure and more particularly, relates to a chess-board patterned bond pad structure on a semiconductor device that is fabricated on a stepped surface formed by a multiplicity of conductive gates and bird's beak field oxide regions such that force incurred in wire bonding can be buffered and a method for fabricating such structure.
BACKGROUND OF THE INVENTION
In the fabrication processes for semiconductor devices, an integrated circuit chip is frequently assembled in a package in a final process step to complete the fabrication process. The assembled package can then be connected to a printed circuit board as part as a large circuit. To establish an electrical communication with the integrated circuit chip, a wire bonding process is frequently used to connect a multiplicity of bond pads on the integrated circuit chip to the outside circuitry.
In a typical IC chip, active circuit elements such as transistors, resistors, etc., are positioned in the central portion, i.e., the active region, of the chip while the bond pads are normally arranged around the periphery of the active region such that active circuit elements are not likely to be damaged during a subsequent bonding process. When a wire bonding process is performed on a bond pad on an IC chip, the process normally entails the bonding of a gold or aluminum wire to the bond pad by fusing the two together with ultrasonic energy. The wire is then pulled away from the bond pad after the bond is formed. During the pulling of the gold wire from the bond, a defect known as bond pad lift-off is frequently encountered. It occurs based on the fact that during the attaching process of a gold wire to a bond pad, a high level of stress is placed on the bond pad. It occurs because a relatively large, heavy bond is placed on top of layers which may not have strong adhesion to the underlying layers. For instance, one factor that affects adhesion between the layers is the common usage of a diffusion barrier layer formed of a material such as TiN for preventing aluminum diffusion into underlying conductive layers during subsequent high temperature processes. The diffusion barrier layer utilized, i.e., TiN, TiW or other alloys, does not have a strong adhesion to the underlying oxide layer in the bond pad. This is only one reason that bond pad lift-off defect occurs. Other reasons such as the high bonding stress and the high pull force also contribute to the lift-off problem. Most lift-off problems occur at an interface between a polycide layer and a field oxide layer.
It is therefore an object of the present invention to provide a bond pad structure that does not have the drawbacks and shortcomings of the conventional bond pad structures used on integrated circuit devices.
It is another object of the present invention to provide a bond pad structure on a semiconductor device that is formed in a chess-board patterned such that bonding stress can be buffered to prevent bond pad lift-off defect from occurring.
It is a further object of the present invention to provide a chess-board patterned bond pad structure that has stress buffered characteristics by first building a multiplicity of bird's beak field oxide regions on a silicon substrate.
It is another further object of the present invention to provide a chess-board patterned bond pad structure on a semiconductor device that has stress buffered characteristics by first building a multiplicity of bird's beak field oxide regions on a silicon substrate, then depositing a conductive material layer on the field oxide regions to form a stepped surface such that bonding stress can be more effectively distributed.
It is still another object of the present invention to provide a chess-board patterned bond pad structure on a semiconductor device that has stress buffered characteristics by first building a multiplicity of bird's beak field oxide regions on a silicon substrate, and then forming a multiplicity of conductive gates on each of the field oxide regions resulting a stepped surface.
It is yet another object of the present invention to provide a chess-board patterned bond pad structure on a semiconductor device that has stress buffered characteristics by first building a multiplicity of bird's beak field oxide regions on a silicon substrate and then forming a multiplicity of polycide gates on each of the field oxide regions resulting in such that, after a metal layer is deposited on top, a stepped surface is formed to more effectively distribute a bonding stress.
It is still another further object of the present invention to provide a method for fabricating a chess-board patterned bond pad structure by first forming a multiplicity of field oxide regions in rows and columns in a surface layer of a silicon substrate and then depositing a conductive material layer on top of the silicon substrate to form a stepped surface prior to the deposition of a metal layer on top.
It is yet another further object of the present invention to provide a method for fabricating a chess-board patterned bond pad structure on a semiconductor device by first forming a multiplicity of bird's beak field oxide regions in the surface of a silicon substrate and then forming a multiplicity of polycide gates on each of the multiplicity of bird's beak field oxide regions prior to the deposition of a metal layer on top.
SUMMARY OF THE INVENTION
In accordance with the present invention, a chess-board patterned bond pad structure on a semiconductor device is provided which consists of a multiplicity of field oxide regions formed in a surface layer of a silicon substrate and a conductive layer deposited on top of the field oxide regions forming a stepped surface prior to the deposition of a metal layer on top to achieve stress buffered characteristics.
In a preferred embodiment, a chess-board patterned bond pad structure that has stress buffered characteristics is provided which includes an electronic substrate, a multiplicity of field oxide regions formed in rows and columns embedded in a surface layer of the electronic substrate while partially protruding from a planar surface of the electronic substrate forming a first stepped surface, a conductive layer deposited on the electronic substrate overlying the multiplicity of field oxide regions forming a second stepped surface conforming to the first stepped surface, and a metal layer overlying the conductive layer conforming to a topography of the conductive layer thus forming a third stepped surface for the bond pad structure adapted for connecting to a bonding wire. The electronic substrate may be a silicon substrate. The multiplicity of field oxide regions may be bird's beak oxide regions grown in a top surface of a silicon wafer in both lateral and transverse directions to form a first stepped surface. The conductive layer deposited may be a non-metallic layer, or a polycide layer. The metal layer may be formed of a material such as Al, AlCu or AlCuSi. The metal layer further reacts with the conductive layer of polycide. The structure may further include a layer of Al or Au on top of the metal layer as wiring to the bond pad.
The chess-board patterned bond pad structure may further include an adhesion layer on top of the metal layer, a metal pad layer formed substantially of AlCuSi on top of the adhesion layer, and a metal wiring layer of substantially Al on top of the metal pad layer. The conductive layer may also be formed into a multiplicity of conductive gates each situated on top of a field oxide region. The multiplicity of conductive gates may further include insulating sidewall spacers formed surrounding the gates.
In another preferred embodiment, a chess-board patterned bond pad structure that has stress buffered characteristics is provided which includes a substrate, a multiplicity of field oxide regions formed in rows and columns embedded in a surfac
Chen Bor-Cheng
Horng J. H.
Wu Lin-June
Yiu Ho-Yin
Chambliss Alonzo
Chaudhuri Olik
Taiwan Semiconductor Manufacturing Company Ltd
Tung & Associates
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