Method for fabricating a semiconductor memory device

Details Method for fabricating a semiconductor memory device Method for fabricating a semiconductor memory device

2002-07-01

2004-08-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S233000

Reexamination Certificate

active

06773986

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for fabricating a semiconductor memory device.
In modern semiconductor memory devices, in particular, in chain FeRAM memories or the like, a plurality of capacitor devices are provided as storage elements in the form of a capacitor configuration in the region of a semiconductor substrate or the like and/or of a passivation region and/or of a surface region thereof.
An objective of the ongoing development of modern semiconductor memory technologies is, inter alia, the formation of the most extensive integration density possible. Conventional semiconductor memory devices that use capacitor devices as storage elements are limited with regard to the integration density to the effect that the capacitor devices used should not fall below a certain minimum size, and, thus, a minimum lateral extent, for their functioning as storage capacitors or storage elements. Consequently, even with minimum distance separating conventional capacitor devices, there is a resultant limit in the area density of storage elements that cannot be undershot. In this case, the respective minimum separating distance is given in each case by the minimum feature size of the respective lithographic technique.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a semiconductor memory device that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that achieves a particularly high integration density in conjunction with functional reliability.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for fabricating a semiconductor memory device. The method includes, forming semiconductor substrate, a passivation region, and/or a surface region with a CMOS structure. A capacitor configuration of a plurality of capacitor devices serving as storage elements is formed in a region of the semiconductor substrate, the passivation region, and/or the surface region. Respective capacitor devices are formed and/or patterned partially and/or locally in a substantially vertically extending fashion with respect to the horizontally extending semiconductor substrate, the passivation region, and/or the surface region, and, as a result, forming and/or patterning a three-dimensional configuration extending partially and/or locally into a third dimension with respect to the semiconductor substrate, the passivation region, and/or the surface region for a respective one of the capacitor devices. A contact connection of the capacitor devices and of the electrode devices is formed with the CMOS structure by plug regions after production of the capacitor devices. Preferably, the method fabricates a chain FeRAM memory.
In the method for fabricating a semiconductor memory device, in particular, a chain FeRAM memory or the like, firstly a semiconductor substrate or the like, a passivation region, and/or a surface region thereof with a CMOS structure are formed. Such a configuration is fundamental for the circuit of the semiconductor memory device. Furthermore, a capacitor configuration of a plurality of capacitor devices serving as storage elements is formed in the region of the semiconductor substrate or the like, the passivation region, and/or the surface region thereof.
Furthermore, in accordance with another mode of the invention, the capacitor device is respectively formed and/or patterned in a fashion extending at least partially and/or locally substantially vertically or perpendicularly to the substrate with respect to the, in particularly, substantially horizontally extending, semiconductor substrate or the like, the passivation region, and/or the surface region thereof. Furthermore, it is provided according to the invention that, as a result, in particular, in each case a substantially three-dimensional configuration or structure and/or an configuration or structure extending at least partially and/or locally substantially into the third dimension with respect to the, in particular, substantially horizontally extending, semiconductor substrate or the like, the passivation region, and/or the surface region thereof, is formed and/or patterned for the respective capacitor device.
It is, thus, a fundamental idea of the method according to the invention to form and/or to pattern the respective capacitor devices such that they run substantially in vertically extending fashion with respect to the surface of the semiconductor substrate or the like. What is thereby achieved is that the integration density and, thus, the area of the entire cell array is no longer dominated by the required area proportion of the electrode areas, but rather ultimately substantially by the resolution and the feature size of the patterning method during the formation of the capacitor configuration. In principle, the possibility is, thus, afforded of orienting the feature size or minimum lateral extent of a capacitor device to the physically required layer thicknesses for the capacitor electrodes and the dielectric.
In such a case, a first and a second electrode device and also a dielectric—substantially provided between the latter—of the respective capacitor device are respectively formed and/or patterned at least partially and/or locally in a fashion extending substantially vertically or perpendicularly to the substrate with respect to the, in particular, substantially horizontally extending, semiconductor substrate or the like, the passivation region, and/or the surface region thereof. This is done such that, in this case, in particular, the sequence of first electrode device, dielectric, and second electrode device of the respective capacitor device is formed at least partially and/or locally in substantially horizontally extending fashion with respect to the, in particular, substantially horizontally extending, semiconductor substrate or the like, the passivation region and/or the surface region thereof, in a form disposed one beside the other in the surface region of the semiconductor substrate and/or of the passivation region thereof.
In the text above and below, the term dielectric always means the central dielectric of the storage capacitor/the capacitor device and/or the so-called node dielectric. This is, in particular, a ferroelectric (SBT, PZT, . . . ), a paraelectric, or the like.
In accordance with a further mode of the invention, the, in particular, substantially horizontally extending, semiconductor substrate or the like, and/or the surface region thereof and, in particular, the CMOS structure are at least partially covered and/or embedded by at least one first substantially top-situated and/or substantially laterally extending passivation region made of a substantially electrically insulating material, in a two-dimensional, large- and/or whole-area manner and/or with a planar surface region. Such a measure creates an isolation between the actual semiconductor substrate and the CMOS structure formed therein, and the capacitor configuration that is to be disposed thereabove. The passivation region is deposited, in particular, in a substantially two-dimensional, large- and/or whole-area manner and/or, in particular, with a planar surface.
In accordance with an added mode of the invention, a contact connection for the capacitor devices to be formed and particularly for their electrode devices to be formed with the CMOS structure is formed by contact regions or plug regions substantially after the formation of the capacitor devices.
In accordance with an additional mode of the invention, at defined first regions and/or at defined first locations in the first, substantially top-situated, passivation region, cutouts are formed, in particular, by a, preferably selective, etching process or the like and/or, in particular, in a manner spaced apart substantially vertically from the level of the semiconductor substrate and/or of the surface region thereof. In such a case, in particular, substantially ele

Affiliated with

Also associated with

Rating

Method for fabricating a semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating a semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3288853