Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-05-02
1998-07-14
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438595, 438675, H01L 218242
Patent
active
057803390
ABSTRACT:
This present invention is a method of fabricating a semiconductor memory cell in a DRAM. This invention utilizes a inter plug technique and nitride sidewall spacers to improve deep node contact etching damage and reduce the number of mask steps for typical landing pad processes. Thus, the method of this invention allows the manufacture of a semiconductor memory cell that reduces the difficulties due to the high aspect ratio of the contact hole of a storage node.
REFERENCES:
patent: 5296400 (1994-03-01), Park et al.
patent: 5332685 (1994-07-01), Park et al.
patent: 5441908 (1995-08-01), Lee et al.
patent: 5492850 (1996-02-01), Ryou
Liang Wen-Jya
Lin Yeh-Sen
Liu Bin
Chaudhari Chandra
Vanguard International Semiconductor Corporation
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