Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-02
2002-10-29
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S297000, C438S296000, C438S294000, C438S221000, C438S218000, C438S197000, C438S424000, C438S430000
Reexamination Certificate
active
06472277
ABSTRACT:
This application claims the benefit of Korean patent application No. 9235/1999, filed Mar. 18, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method for fabricating the same with an improved short channel effect and reduced punch-through caused during channel formation.
2. Discussion of the Related Art
A related art semiconductor device and method for fabricating the same will be explained with reference to the attached drawings.
Referring to
FIG. 1
, a related art semiconductor device includes a semiconductor substrate
11
, a gate insulating film
12
on the semiconductor substrate
11
, and a gate electrode
13
a
on the gate insulating film
12
. Insulating sidewalls
16
are formed at both sides of the gate electrode
13
a
, and source and drain impurity regions
17
of an LDD (Lightly Doped Drain) structure are formed in a surface of the semiconductor substrate
11
on both sides of the gate electrode
13
a.
FIGS. 2A-2D
illustrate cross-sections showing a related art method for fabricating the semiconductor device of FIG.
1
.
Referring to
FIG. 2A
, the related art method for fabricating a semiconductor device first forms the gate insulating film
12
and a polysilicon film
13
on the semiconductor substrate
11
. A photoresist
14
is coated on the polysilicon film
13
, and subjected to patterning after exposure and development, to define a gate region.
As shown in
FIG. 2B
, the patterned photoresist
14
is used as a mask to selectively remove the polysilicon film
13
and the gate insulating film
12
, forming the gate electrode
13
a.
As shown in
FIG. 2C
, the patterned photoresist
14
is removed, and the gate electrode
13
a
is used as a mask when n-type impurity ions are doped into an entire surface of the semiconductor substrate
11
, forming LDD regions
15
in the surface of the semiconductor substrate
11
at both sides of the gate electrode
13
a.
As shown in
FIG. 2D
, an insulating film is formed on an entire surface of the semiconductor substrate
11
, including the gate electrode
13
a
, and etched back, forming the insulating sidewalls
16
at both sides of the gate electrode
13
a
. Then, the gate electrode
13
a
and the insulating sidewalls
16
are used as a mask to heavily dope n-type impurity ions into the entire surface of the semiconductor substrate
11
, forming the source and drain impurity regions
17
in the surface of the semiconductor substrate
11
on both sides of the gate electrode
13
a.
However, the related art semiconductor device and the method for fabricating the same have the following problem. Due to higher density of devices, a channel becomes shorter following a scaling-down of the gate electrode. DIBL (Drain Induced Barrier Lowering) characteristic of the transistor is significantly lowered, which likely generates an electron punch-through.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor device and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor device and a method for fabricating the same that improve the short channel effect, as well as to reduce punch-through caused during channel formation.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect of the present invention there is provided a semiconductor device including a semiconductor substrate having a trench in its surface, an insulating film in the trench, a doped conductive layer on the insulating film, a gate insulation film and a gate electrode on the doped conductive layer over the trench, and source and drain impurity regions in the surface of the semiconductor substrate at sides of the gate electrode.
In another aspect of the present invention, there is provided a method for fabricating a semiconductor device, the method including the steps of forming a first trench in a surface of a semiconductor substrate, burying an insulating film in the first trench, selectively removing the insulating film to form a second trench in the surface of the semiconductor substrate, burying a doped conductive layer in the second trench, forming a gate insulation film and a gate electrode on the doped conductive layer, and forming source and drain impurity regions in the surface of the semiconductor substrate at sides of the gate electrode.
In another aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate, a trench in a surface of the semiconductor substrate, an insulating layer over the trench, a doped polysilicon layer on the insulating layer, a gate insulation layer on the doped polysilicon layer over the trench, a gate electrode on the doped polysilicon layer, and source and drain impurity regions in the surface of the semiconductor substrate at sides of the gate electrode.
In another aspect of the present invention, there is provided a method for fabricating a semiconductor device, the method including the steps of forming a first trench in a surface of a semiconductor substrate, forming an insulating layer in the first trench, selectively removing the insulating layer to form a second trench in the surface of the semiconductor substrate, forming a doped polysilicon layer in the second trench, forming a gate insulation layer and a gate electrode on the doped polysilicon layer, and forming source and drain impurity regions in the surface of the semiconductor substrate at sides of the gate electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5182619 (1993-01-01), Pfiester
patent: 5453635 (1995-09-01), Hsu
patent: 5798278 (1998-08-01), Chan
patent: 6100146 (2000-08-01), Gardener
patent: 6200841 (2001-03-01), Kim
patent: 6218315 (2001-04-01), Ballamine
Back Young Kum
Cheong Yeon Woo
Duong Khanh B.
Jr. Carl Whitehead
Morgan & Lewis & Bockius, LLP
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