Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-30
2001-02-06
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S622000, C438S256000, C438S964000
Reexamination Certificate
active
06184079
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, more particularly to a dynamic random access memory(DRAM) having a stacked capacitor.
BACKGROUND OF THE INVENTION
In the DRAM industry, as DRAMs increase in memory cell density, there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally there is a continuing goal to further decrease cell area. Generally, the capacitance of the capacitor directly related to the surface area of the capacitor. For this reason, there is continuous challenge to increase the surface area of the capacitor, i.e., conventional two-dimensional structure to three-dimensional structure(trench or stacked capacitor). The widely adopted stacked capacitor includes for example cylindrical and fin type capacitor.
From the fabrication sequence point view, the structure of the capacitor mainly classified into COB(capacitor over bit line) structure and CUB(capacitor under bit line) structure. The significant difference between them is the time when the capacitor is formed, i.e., after forming the bit line(COB) or before forming the bit line(CUB).
The COB structure has an advantage that the capacitor can be formed without regard to the bit line process margin since the capacitor is formed after the bit line formation. Therefore, it has a relatively increased capacitance in comparison with the CUB structure. On the contrary, in the COB structure, the bit line design rule put a limit on process margin for buried contacts formation for electrical connection to storage electrode and switch transistor.
FIG. 1
is a cross-sectional view showing a conventional DRAM structure. In the method for fabricating the conventional DRAM structure shown in
FIG. 1
, a bit line
130
in a cell array region is made of conductive material and at the same time(i.e., at the same process step) an interconnection wiring line
130
a
in core/peripheral region are formed by using the same conductive material as the bit line. By doing this, the conventional method can simplify the process and reduce the cost. Capping layers
132
and
134
for example silicon nitride layer(Si
3
N
4
) are formed to coat exposed portion of the bit line
130
and the interconnection wiring line
130
a
so as to protect the bit line
130
and the interconnection wiring line
130
a
during subsequent etching process. After that, lower electrode
136
(i.e., storage electrode) of the capacitor, dielectric film, and upper electrode
140
(i.e., plate electrode) are sequentially formed.
Herein, the step of forming the storage electrode
136
includes depositing a conductive material over the semiconductor substrate and etching the conductive material to form the storage electrode
136
using predetermined pattern. Because the conductive material in the core/peripheral region must be completely removed away, over etch can be conducted. Therefore, in the step of etching the conductive material, the capping layers
132
and
134
in the core/peripheral region can be etched and further in the steps of forming the dielectric film and the plate electrode
140
can be etched, thereby causing open fail of the interconnection wiring line
130
a
. But also, in the case of reducing the etching rate in the core/peripheral region so as to overcome above problems, material residues occurs between the bit lines
130
or the interconnection wiring lines
130
a
, thereby making it difficult to form contact hole.
SUMMARY OF THE INVENTION
The present invention provides an improved method for fabricating a semiconductor memory device. A key feature of the invention is forming an interconnection wiring line in core/peripheral region before bit line formation in cell array region.
Accordingly, an object of the present invention is to provide a method for fabricating a semiconductor memory device, being capable of preventing over etching of a capping layer which is formed on the interconnection wiring line.
It is a further object of the invention to provide a method for fabricating the semiconductor memory device, being capable of preventing open fail between the interconnection wiring line.
It is yet another object of the invention to provide a method for fabricating the interconnection wiring line, being capable of improving the process margin in the core/peripheral region.
Other aspect, objects, and the several advantages of the present invention will be apparent to one skilled in the art from a reading of the following disclosure and appended claims.
To achieve this and other advantages and in accordance with the purpose of the present invention, a transistor having source/drain and gate is formed over a semiconductor substrate in cell array and core/peripheral regions, respectively. A first interlayer insulating film is formed over the semiconductor substrate including the transistor. A conductive pad for a bit line and an interconnection wiring line are simultaneously formed by etching the first interlayer insulating film and electrically connected to the source/drain in the cell array region and to the transistor in the core/peripheral regions, respectively. A second interlayer insulating film is formed over the first interlayer insulating film including the conductive pad and the interconnection wiring. A contact plug for a storage electrode is formed by etching the second and first interlayer insulating films in the cell array region and electrically connected to the source/drain of the transistor in cell array region. A conductive layer for the bit line is formed by etching the second interlayer insulating film in the cell array region and electrically connected to the conductive pad. A capping layer is formed to coat exposed portion of the conductive layer. The storage electrode is formed over the second interlayer insulating film such that electrically connected to the contact plug.
To achieve this and other advantages and in accordance with the purpose of the present invention, a transistor having source/drain and gate is formed over a semiconductor substrate in cell array and core/peripheral regions, respectively. A first interlayer insulating film is formed over the semiconductor substrate including the transistor. A conductive pad for a bit line is formed by etching the first interlayer insulating film in the cell array region and electrically connected to the source/drain in the cell array region. A second interlayer insulating film is formed over the first interlayer insulating film including the conductive pad. An interconnection wiring line is formed by etching the second and first interlayer insulating films in the core/peripheral region and electrically connected to the transistor in the core/peripheral region. A third interlayer insulating film is formed over the second interlayer insulating film including the interconnection wiring. A contact plug for a storage electrode is formed by etching the third, second, and first interlayer insulating films in the cell array region and electrically connected to the source/drain of the transistor in cell array region. A conductive layer for the bit line is formed by etching the third and second interlayer insulating films in the cell array region and electrically connected to the conductive pad. A capping layer is formed to coat exposed portion of the conductive layer. The storage electrode is formed over the third interlayer insulating film such that electrically connected to the contact plug.
To achieve this and other advantages and in accordance with the purpose of the present invention, a transistor having source/drain and gate is formed over a semiconductor substrate in cell array and core/peripheral regions, respectively. A first interlayer insulating film is formed over the semiconductor substrate including the transistor. An interconnection wiring line is formed by etching the first interlayer insulating film in the core/peripheral region and electrically connected to the transistor in the core/peripheral region. A second interlayer insulating film is
Fahmy Wael
Kebede Brook
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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