Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-01
2001-07-17
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S948000, C438S949000
Reexamination Certificate
active
06261898
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for a salicide gate.
2. Description of the Related Art
There is a continuing effort in the semiconductor industry to increase the integration of a semiconductor device, for example, a Dynamic Random Access Memory (DRAM) device. The DRAM device is composed, in part, of an array of memory cells. Each RDAM cell is formed with a capacitor for storing an electrical charge representing a bit of data, and a transistor, controlled through a word line, for selectively coupling the capacitor to a bit line. The increase of the integration is normally accompanied by a decrease of the device dimension. As a result, the dimension of a polysilicon gate is decreased, leading to an increase of the gate resistance and the gate response time.
Currently, the common approach to reduce the gate response time and to increase the operational speed of a device is to form a low contact resistance layer, for example, a metal silicide layer, on the polysilicon gate in order to avoid the gate electrical circuit delay induced by the higher contact resistance. The resulting polysilicon/metal silicide gate has been typically formed through a self-aligned silicide process, for example, as a tungsten salicide (WSi) gate.
FIGS. 1A
to
1
B are cross-sectional views showing the processing of a tungsten salicide gate according to the prior art.
As shown in
FIG. 1A
, a substrate
100
, comprising device isolation structures are to define the active region, is provided. A gate oxide layer
110
and a polysilicon gate
120
, wherein spacers
130
are formed on the sidewalls of the polysilicon gate, are formed on the substrate
100
. An ion implantation is then conducted to form the source/drain regions
140
in the substrate
100
on both sides of the polysilicon gate
120
. Thereafter, a metal layer
150
, for example, a tungsten layer, is deposited on the substrate
100
.
Continuing to
FIG. 1B
, a thermal process is conducted to induce a reaction between the metal layer
150
(as shown in
FIG. 1A
) and the source/drain regions
140
and the polysilicon gate
120
, respectively, to form a salicide layer
160
on the source/drain region
140
and a salicide layer
160
on the polysilicon gate
120
. The unreacted metal layer
150
, as shown in
FIG. 1A
, is subsequently removed to complete the manufacturing of a tungsten salicide gate
180
.
This conventional approach in forming a salicide gate, however, has its disadvantages, especially when the capacitor is being used as a dynamic random access memory (DRAM) device. Although the gate resistance is reduced in the conventional approach, a low resistance salicide layer is also formed on the surfaces of the adjoining source/drain regions. A higher current leakage is thus resulted at the source/drain regions, which would lead to the loss of the stored data and adversely affecting the data retention characteristics of the DRAM cell. The DRAM cell must therefore be refreshed frequently and the operational efficiency of the device is thereby reduced.
SUMMARY OF THE INVENTION
Based on the foregoing, the present invention provides a fabrication method for salicide gates, which is applicable to a DRAM device, wherein a substrate comprising a memory cell region and a logic region, is provided. A plurality of polysilicon gates and adjoining source/drain regions are formed in both the memory cell region and the logic region. A conformal protection layer and a first photoresist layer are sequentially formed on the source/drain regions and the polysilicon gates. A blanket defocus exposure is then conducted, wherein only the portion of the first photoresist layer above the top surface of the polysilicon gates is subsequently removed. After this, the exposed protection layer is removed, followed by forming a second photoresist layer on the memory cell region. Using the second photoresist layer as a mask, the remaining protection layer in the logic region is removed. A self-aligned silicide processing is then conducted to form the salicide gates.
According to the preferred embodiment of the present invention, the salicide layers are selectively formed on the polysilicon gates in both the logic and the memory cell regions and on the source/drain regions in the logic region only. The problem of charge leakage from the source/drain regions, leading to a loss of the stored data, is thus prevented. The problem of increasing the refreshing frequency of the DRAM cell is thus avoided and the operational efficiency of the device can be maintained.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
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patent: 5863820 (1999-01-01), Huang
patent: 5998252 (1999-12-01), Huang
patent: 6004843 (1999-12-01), Huang
patent: 6015730 (2000-01-01), Wang et al.
patent: 6015748 (2000-01-01), Kim et al.
patent: 6037222 (2000-03-01), Huang et al.
patent: 6162675 (2000-12-01), Hwang et al.
patent: 6171942 (2001-01-01), Lee et al.
Booth Richard
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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