Method for fabricating a patterned layer

Details Method for fabricating a patterned layer Method for fabricating a patterned layer

2001-12-26

2002-12-17

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S239000, C438S393000, C438S396000

Reexamination Certificate

active

06495415

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for fabricating a patterned layer, and in particular, to a method for fabricating a patterned layer in an integrated circuit.
Over the last 25 years, the storage density of DRAM (Dynamic Random Access Memory) memory modules has quadrupled from one generation to the next. However, the basic design of an elemental memory cell and the materials used to construct the memory cell have remained substantially unchanged. A DRAM memory cell includes a transistor and a capacitor that stores the charge required to represent the information, just as it did 25 years ago. The capacitor of the memory cell has electrodes made from doped silicon or polysilicon and a dielectric layer made of silicon dioxide and/or silicon nitride that is arranged between the electrodes.
To be able to reproducibly read the charge stored in a capacitor, the capacitance of the capacitor should be at least approximately 30 fF. At the same time, it has been necessary, and remains necessary, to constantly reduce the lateral extent of the capacitor, in order to be able to achieve the abovementioned increase in the storage density. These inherently contradictory demands imposed on the capacitor of the memory cell have led and continue to led to increasingly complex structuring of the capacitor (“trench capacitors”, “stack capacitors”, “crown-shaped capacitors”), in order to be able to provide a sufficiently large capacitor surface despite the continually decreasing lateral extent of the capacitor. However, this makes fabrication of the capacitor increasingly complex and therefore increasingly expensive.
A further way of achieving a capacitor with a sufficient capacitance is to use different materials between the capacitor electrodes. Therefore, in recent times new materials, in particular paraelectrics and ferroelectrics, have been used between the capacitor electrodes of a memory cell instead of the conventional silicon oxide/silicon nitride. These new materials have a considerably higher relative dielectric constant (>20) than the conventional silicon oxide/silicon nitride (<8). Therefore, when these materials are used to obtain the same capacitance in a memory cell with same lateral extent, the capacitor area required and therefore the complexity of the patterning of the capacitor required can be reduced considerably. By way of example, barium strontium titanate (BST, (Ba, Sr) TiO
3
), lead zirconate titanate (PZT, Pb(Zr, Ti) O
3
) or lanthanum-doped lead zirconate titanate, or strontium bismuth tantalate (SBT, SrBi
2
Ta
2
O
9
) are used.
In addition to conventional DRAM memory modules, ferroelectric random access memories, known as FRAMs, will play an important role in the future. Compared to conventional memory arrangements, such as for example, DRAMs and SRAMs (Static Random Access Memories), ferroelectric memory arrangements have the advantage that the stored information is not lost even when the voltage or current supply is interrupted, but rather remains stored. This non volatile state of ferroelectric memory arrangements is based on the fact that, when using ferroelectric materials, the polarization which is applied using an external electric field is substantially retained even after the external electric field has been disconnected. The abovementioned new materials, such as barium strontium titanate (BST, (Ba, Sr) TiO
3
), lead zirconate titanate (PZT, Pb(Zr, Ti)O
3
) or lanthanum-doped lead zirconate titanate, or strontium bismuth tantalate (SBT, SrBi
2
Ta
2
O
9
) are also used for ferroelectric memory arrangements.
Unfortunately, when these new paraelectrics or ferroelectrics are used, new electrode materials must also be used. The new paraelectrics or ferroelectrics are usually deposited on electrodes that are already present (bottom electrodes). The processing takes place at high temperatures, and at these temperatures, the materials which usually make up the capacitor electrodes, for example doped polysilicon, are readily oxidized and lose their electrically conductive properties, which would lead to a failure of the memory cell.
Because of their good resistance to oxidation and/or the formation of electrically conductive oxides, 4d and 5d transition metals, in particular platinum metals (Ru, Rh, Pd, Os, Ir, Pt), and in particular platinum itself, appear to be promising candidates that could replace doped silicon/polysilicon as the electrode material.
Unfortunately, it has been found that the abovementioned materials, which are now being employed in integrated circuits, are very difficult or even impossible to etch chemically. The material that is removed by etching, even when using “reactive” gases, is attributable predominately or almost exclusively to the physical component of the etching.
Patterning of the materials used hitherto has generally been carried out with plasma-assisted anisotropic etching methods. In this case, physical-chemical methods are employed, in which gas mixtures including one or more reactive gases, such as for example, oxygen, chlorine, bromine, hydrogen chloride, hydrogen bromide or halogenated hydrocarbons and inert gases (e.g. Ar, He) are used. These gas mixtures are generally excited in an alternating electromagnetic field at low pressures, with the result that the gas mixture is converted into a plasma.
The positive ions of the plasma then impinge virtually perpendicularly on the layer that is to be patterned, allowing good reproduction of a mask resting on the layer that is to be patterned. Photoresists are usually used as the mask materials, since they can be patterned relatively easily by means of an exposure step and a development step. The physical component of the etching is effected by the pulsed and kinetic energy of the impinging ions (e.g. C12+, Ar+). In this way, chemical reactions
between the layer that is to be patterned and the reactive gas particles (ions, molecules, atoms, radicals) leading to the formation of volatile reaction products, are initiated or enhanced (chemical component of the etching). These chemical reactions between the substrate particles and the gas particles are responsible for the high etching selectivity of the etching process.
Since the chemical component is small or even absent when etching the above materials, in particular, when etching the electrode material, the amount of material removed from the layer to be patterned by etching is of the same order of magnitude as the amount of material removed from the mask or the underlying layer (etching stop layer). Thus, the etching selectivity with respect to the etching mask or the underlying layer is generally low (between approximately 0.3 and 3.0). Consequently, the erosion of masks with inclined flanks and the inevitable formation of bevels on the masks means that the patterning will have a low-dimensional accuracy. Furthermore, particularly when carrying out an overetching step, the underlying layer is etched to a considerable extent, and the result is sloping etched flanks which are very difficult to control. Consequently, very small electrodes (basic surface area of the electrode=F2, F=smallest feature size which can be fabricated using a defined technique) can only be produced with considerable effort.
To improve or avoid the etching of layer materials that are difficult to etch, Published European Patent Application EP 859 405 A2, Published European Patent Application EP 867 926 A1, and Published German Patent Application DE 197 03 205 A1 describe methods in which raised capacitor electrodes, selective silicide regions or combined precious metal
on-precious metal structures are formed.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a patterned layer in which the abovementioned problems with occur in the physical-chemical etching processes are considerably reduced or avoided altogether.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricatin

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