Method for fabricating a nitrided silicon-oxide gate dielectric

Details Method for fabricating a nitrided silicon-oxide gate dielectric Method for fabricating a nitrided silicon-oxide gate dielectric

2002-07-01

2004-08-24

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S775000, C438S786000, C438S787000, C438S776000

Reexamination Certificate

active

06780720

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the manufacture of semiconductor devices; more specifically, it relates to a method of fabricating a nitrided silicon-oxide gate dielectric.
BACKGROUND OF THE INVENTION
The trend in integrated circuits is toward higher performance, higher speed and lower cost. Correspondingly, device dimensions and element sizes are shrinking and gate dielectrics must scale accordingly. As physical gate dielectric thickness has decreased, the need for a higher dielectric constant and less leaky gate dielectric has arisen. In advanced metal oxide semiconductor field effect transistors (MOSFETs) silicon oxynitride (SiO
x
N
y
) layers are used as a gate dielectric. MOSFET transistors include a channel region formed in a silicon substrate, an N or P doped polysilicon gate formed on top of a thin gate dielectric layer and aligned over the channel region and source/drain regions formed in the silicon substrate on either side of the channel region.
However, there are several problems associated with SiOxN
y
layers that affect the performance of devices having a SiO
x
N
y
gate dielectric. These problems are a result of the processes used to fabricate the SiO
x
N
y
layer and the distribution of nitrogen in the layer. SiOxNy layers fabricated using conventional plasma nitridation processes have poor reliability as a result of low time dependent dielectric breakdown (T
BD
) and charge-to-breakdown (Q
BD
). The degradation in reliability is caused by plasma induced dangling bonds in the dielectric and at the dielectric-silicon interface. Further, the nitrogen concentration in SiO
x
N
y
layers fabricated using conventional plasma and thermal nitridation processes is not uniformly distributed throughout the layer but is concentrated at the SiO
x
N
y
/Si interface causing large threshold voltage (V
T
) shifts; the shifts of p-channel field effect transistors (PFETs) being larger than that of N-channel field effect transistors (NFETs). Both mechanisms described above will cause a degradation in the channel mobility. Both mechanisms described above will also cause an increase in negative bias temperature instability (NBTI) which induces V
T
and frequency shifts after stressing. Additionally, the relative lack of nitrogen near the surface of conventional SiO
x
N
y
layers results in increased boron penetration from the gate electrode (in PFETs) into the SiO
x
N
y
layer which can degrade Tbd and Qbd as well as influence across-wafer V
T
uniformity.
Therefore, there is a need for a method of fabricating a SiO
x
N
y
layer having a relatively uniform nitrogen concentration throughout its thickness, high mobility and high Tbd and Qbd, while forming a layer with realtively high nitrogen content to lower leakage current through the gate dielectric when the device is turned off.
SUMMARY OF THE INVENTION
A first aspect of the present invention is A method of fabricating a gate dielectric layer comprising: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; exposing the silicon dioxide layer to a plasma nitridation to convert the silicon dioxide layer into a silicon oxynitride layer; and performing a spiked rapid thermal anneal of the silicon oxynitride layer.
A second aspect of the present invention is a method of fabricating a MOSFET, comprising: providing a silicon substrate; forming a silicon dioxide layer on a top surface of the silicon substrate; exposing the silicon dioxide layer to a plasma nitridation to convert the silicon dioxide layer to a silicon oxynitride layer; performing a spiked rapid thermal anneal of the silicon oxynitride layer; forming a polysilicon gate on the annealed silicon oxynitride layer aligned over a channel region in the silicon substrate; and forming source/drain regions in the silicon substrate, the source drain regions aligned to the polysilicon gate.


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