Method for fabricating a MOS transistor using a self-aligned...

Details Method for fabricating a MOS transistor using a self-aligned... Method for fabricating a MOS transistor using a self-aligned...

2002-04-22

2003-10-21

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S592000, C438S595000

Reexamination Certificate

active

06635539

ABSTRACT:

RELATED APPLICATION
This application claims priority from Korean Patent Application No. 2001-23446, filed on Apr. 30, 2001, the contents of which are incorporated herein by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a MOS transistor using a self-aligned silicide technique.
BACKGROUND OF THE INVENTION
As semiconductor devices become more highly integrated, the line width of a gate electrode and the depth of source/drain regions in a MOS transistor have been reduced. Thus, the operating speed of the MOS transistor becomes slower, since resistances of both the gate electrode and the source/drain regions increase. Also, if the depths of the source/drain regions become shallower, the semiconductor substrate under the source/drain regions may be exposed due to over-etching during the formation of contact holes to expose the source/drain regions. Further, when a metal layer is formed in the contact holes that expose the shallow source/drain regions, a junction-spiking phenomenon more easily occur, where the metal layer penetrates the source/drain regions. Accordingly, a salicide technique is widely used in semiconductor fabrication processes. According to the salicide technique, a metal silicide layer is selectively formed on the gate electrode and the source/drain regions.
The metal silicide layer can be classified into three categories. One is a refractory metal silicide layer, another is a group-VIII metal silicide layer and the other is a titanium silicide layer. Here, the refractory metal silicide layer exhibits higher resistivity than the group-VIII metal silicide layer and the titanium silicide layer. Thus, it is preferable to use the titanium silicide layer or the group-VIII metal silicide layer in order to reduce the resistances of the gate electrode and the source/drain regions. The group-VIII metal silicide layer comprises a cobalt silicide layer, a platinum silicide layer, a palladium silicide layer and a nickel suicide layer.
However, if the cobalt silicide layer is formed on the source/drain regions, junction leakage current characteristics of the source/drain regions may be degraded. Thus, it is preferable that the cobalt silicide layer be formed only on the gate electrode. In particular, the cobalt silicide layer exhibits less variation in resistivity due to variations of the line width of the cobalt silicide layer than the titanium silicide layer. Therefore, a technique employing the cobalt silicide layer only on the gate electrode is widely used in a highly integrated semiconductor device having a narrow line width.
FIGS. 1 through 5
are cross-sectional views illustrating a conventional method of fabricating a MOS transistor. In each of the drawings, the reference characters “a” and “b” represent a cell array region and a peripheral circuit region, respectively.
Referring to
FIG. 1
, a device isolation layer
3
is formed in a predetermined region of a semiconductor substrate
1
to define an active region thereof. A gate insulation layer
5
is formed on the active region. A gate electrode layer and a silicidation resistant layer are sequentially formed on the entire surface of the semiconductor substrate having the gate insulation layer
5
. The silicidation resistant layer and the gate electrode layer are successively patterned to form a first gate pattern
10
a
and a second gate pattern
10
b
in the cell array region “a” and in the peripheral circuit region “b”, respectively. Thus, each of the first and second gate patterns
10
a
and
10
b
includes a gate electrode
7
and a silicidation resistant layer pattern
9
, which are sequentially stacked. The first gate pattern
10
a
(extends across) the active region in the cell array region “a” and the second gate pattern
10
b
extends across the active region in the peripheral circuit region “b”.
Referring to
FIG. 2
, an insulation spacer
11
is formed on the sidewalls of the first and second gate patterns
10
a
and
10
b.
An etch stop layer
13
, e.g., a silicon nitride layer, is then formed on the entire surface of the resulting structure having the spacer
11
formed thereon. An interlayer insulation layer
15
is formed on the etch stop layer
13
.
Referring to
FIG. 3
, the interlayer insulation layer
15
is planarized to expose the etch stop layer
13
on the first and second gate patterns
10
a
and
10
b
using chemical mechanical polishing (CMP). At this time, a density of MOS transistors in the peripheral circuit region “b” is lower than that in the cell array region “a”. Thus, as shown in
FIG. 3
, a dishing phenomenon occurs in the peripheral circuit region “b”. As a result, a first planarized interlayer insulation layer
15
a
formed in the cell array region “a” has a uniform thickness, while a second planarized interlayer insulation layer
15
b
formed in the peripheral circuit region “b” has a non-uniform thickness. That is, a region
17
having a thin planarized interlayer insulation layer can be formed on the active region and the device isolation layer
3
in the peripheral circuit region “b”. If the dishing phenomenon occurs severely, the device isolation layer
3
and the active region in the peripheral circuit region “b” may be exposed or severely damaged.
Referring to
FIG. 4
, the exposed etch stop layer
13
and the silicidation resistant layer patterns
9
thereunder are etched to expose the gate electrodes
7
in the cell array region “a” and the peripheral circuit region “b”. A cobalt layer
19
is formed on the entire surface of the resulting structure where the gate electrodes
7
are exposed.
Referring to
FIG. 5
, a semiconductor substrate having the cobalt layer
19
is annealed to form a cobalt silicide layer
19
a
on the surfaces of the gate electrodes
7
. Then, the unreacted portions of the cobalt layer
19
that remain on the first and second planarized interlayer insulation layers
15
a
and
15
b
are selectively removed.
According to the conventional technique described above, a planarization process such as the CMP process is required in order to selectively form the cobalt silicide layer only on the gate electrodes. Thus, severe damage to the active region and the device isolation layer in the peripheral circuit region may result from a dishing phenomenon. Also, because a metal silicide layer such as the cobalt silicide layer is not formed on the source/drain regions of the MOS transistor, it is very difficult to reduce resistivity of the source/drain regions. Further, if shallow source/drain regions are formed, a process margin for the over-etching is decreased during the formation of contact holes to expose the source/drain regions. In other words, if the etching process for forming the contact holes is excessively performed, a junction-spiking phenomenon may occur.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a MOS transistor that can selectively form a first metal silicide layer that can reduce junction spiking on the surface of source/drain regions as well as a second metal silicide layer having a low variation of resistivity due to the variation of line width of the gate electrode in accordance with one embodiment of the present invention.
The present invention also provides a method for fabricating a MOS transistor that can selectively form first and second metal silicide layers, which are different from each other, on a gate electrode and source/drain regions, respectively, without using a planarization process in accordance with another embodiment of the present invention.
Preferably, the first metal silicide layer is formed of a material layer that is suitable for preventing junction spiking, and the second metal silicide layer is formed of a material layer that has a lower variation of resistivity than the first metal silicide layer due to the variation of line width of the gate electrode. This method includes forming a gate electrode and a silicidation resistant layer patter

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