Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-21
2001-11-13
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S201000, C438S211000
Reexamination Certificate
active
06316315
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a memory cell having at least one MOS transistor. The transistor contains a source, a first gate electrode, a second gate electrode, a drain and a channel. The first gate electrode is insulated and can contain an electric charge and a control voltage can be applied to the second gate electrode. The source, the drain and the channel are formed by differently doped regions of a semiconductor substrate and at least one dielectric layer which forms a gate dielectric is situated between the semiconductor substrate and the gate electrodes.
The invention furthermore relates to a method for fabricating such a memory cell.
Such a memory cell is described in U.S. Patent No. 5,242,848. In this case, the first gate electrode extends in a planar manner on a dielectric layer and has a tip. The second gate electrode has a plurality of regions, a lower region being disposed on the same dielectric layer as the first gate electrode and an upper region of the second gate electrode is disposed above the first gate electrode in regions. This configuration produces locally a particularly large electric field gradient on the surface of the first gate electrode. A tip effect promotes Fowler-Nordheim tunneling. Fowler-Nordheim tunneling involves charge transport through an insulator. The charge transport through the insulator is generally dependent to a great extent on the applied electric field. In the case of Fowler-Nordheim tunneling, the electric current density j has the particular dependence j=C
1×&egr;
2
exp (−&egr;
0
/&egr;)where &egr; is the electric field strength and C
1
and &egr;
0
are constants dependent on a effective mass of the charge carriers and a height of a barrier layer. By virtue of the high electric field density, the memory cell of the generic type can be electrically erased in a particularly simple manner.
It has been shown, however, that, for feature sizes of 0.25 &mgr;m or less, the memory cell does not have the necessary reliability for memory cells.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell having a MOS transistor and a method for fabricating it which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which is realizable with feature sizes of 0.25 &mgr;m or less and is intended to be able to be fabricated in the simplest possible manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell, which includes a substrate having differently doped regions and at least one MOS transistor formed on the substrate. The MOS transistor has a source and a first gate electrode being an insulated first gate electrode that can contain an electric charge. The first gate electrode additionally has at least one tip. A second gate electrode is provided for receiving a control voltage and faces the tip of the first gate electrode. The second gate electrode has a first region penetrating into the substrate and a second region projecting above the substrate. The transistor further has a drain and a channel; the source, the drain and the channel are formed in the differently doped regions of the substrate; and at least one dielectric layer forming a gate dielectric is disposed between the substrate and the first and second gate electrodes.
According to the invention, the object is achieved by virtue of the fact that a memory cell of the generic type is furnished such that the second gate electrode, at least in a region, penetrates into the semiconductor substrate. The first gate electrode has a tip facing the second gate electrode.
Preferably, the second gate electrode is at least partially disposed in the trench along whose sidewall a conductive channel can form. The tip of the first gate electrode is disposed at the edge of the trench.
The invention provides for the MOS transistor of the memory cell to be configured in such a way that it has two gate electrodes which are spatially separate from one another, the first gate electrode containing a programmed-in electric charge, and the second gate electrode being connected to a line. In this case, the second gate electrode is configured in such a way that it can penetrate entirely, or in a partial region, into the semiconductor substrate.
The first gate electrode is preferably configured as a floating gate electrode. The term floating gate electrode indicates that the first gate electrode can be provided with a variable electric charge. The first gate electrode is situated at least in regions between the second gate electrode and the channel of the MOS transistor. By virtue of this configuration, the threshold voltage of the memory cell having the MOS transistor and the floating gate electrode depends on the charge situated on the floating gate electrode.
A preferred embodiment of the memory cell according to the invention is distinguished by the fact that the source is disposed more deeply in the semiconductor substrate than the drain. In addition, the second gate electrode penetrates into the semiconductor substrate in such a way that the second gate electrode is situated above the source at least in sections.
In accordance with an added feature of the invention, the second gate electrode has at least one recess formed therein and the tip penetrates into the recess in the second gate electrode.
It is particularly advantageous that the second gate electrode, in a further region, projects above the semiconductor substrate.
A particularly compact cell array can be achieved by virtue of the fact that the first gate electrode runs parallel to the second gate electrode at least in sections.
This makes it possible for a single gate electrode to drive two preferably vertical MOS transistors. The gate electrode is the select gate electrode (Select Gate), which is designated as the second gate electrode in this case.
A tip effect can be achieved in a particularly favorable manner by virtue of the fact that that region of the second gate electrode which penetrates into the semiconductor substrate is formed by a vertical projection of the second gate electrode, and that another region of the second gate electrode extends essentially parallel to a surface of the semiconductor substrate.
A compact configuration in which the second gate electrode (Select Gate) drives two first (floating) gate electrodes can be obtained in a particularly simple and expedient manner by virtue of the fact that the first gate electrode contains a section, which extends parallel to the vertical part of the second gate electrode.
A configuration with a pronounced tip effect and correspondingly promoted Fowler-Nordheim tunneling can be obtained by virtue of the fact that the first gate electrode extends essentially parallel to a surface of the semiconductor substrate, and that the first gate electrode has at least one tip in another region, which is oriented vertically with respect to the semiconductor substrate.
A further increase in the tip effect can be obtained by virtue of the fact that the tip of the first gate electrode penetrates into at least one recess in the second gate electrode.
The invention furthermore relates to a method for fabricating a memory cell having at least one MOS transistor. The method includes depositing a first dielectric layer for forming a first gate dielectric, a first electrically conductive layer for forming a first gate electrode, a second dielectric layer and a second electrically conductive layer for forming a second gate electrode on a semiconductor substrate. In addition, differently doped regions are formed in the semiconductor material for creating a source, a drain and a channel. The method is distinguished according to the invention by the fact that a tip is produced on the first electrically conductive layer, and that the second gate electrode is produced in such a way that it, at least in a region, penetrates into the semiconductor substrate.
The method can be carried out in a parti
Hofmann Franz
Willer Josef
Greenberg Laurence A.
Infineon - Technologies AG
Le Vu A.
Lerner Herbert L.
Owens Beth E.
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