Method for fabricating a high-bias semiconductor device

Details Method for fabricating a high-bias semiconductor device Method for fabricating a high-bias semiconductor device

1998-11-20

2000-09-12

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438510, 438514, 438527, 257333, H01L 21336

Patent

active

061177385

ABSTRACT:
A method for fabricating an improved structure of a high-bias device includes forming multiple doped wells between source/drain regions and a P-type substrate. The doped wells have an increasing order of dopant density from the P-type substrate for the P-type dopant or from a first N-type well for an N-type dopant. The doped multiple wells enclose the source/drain regions so that the source/drain regions do not directly contact with the substrate.

REFERENCES:
patent: 4717679 (1988-01-01), Baliga et al.
patent: 5242841 (1993-09-01), Smayling et al.
patent: 5304827 (1994-04-01), Malhi
patent: 5306652 (1994-04-01), Kwon et al.
patent: 5444002 (1995-08-01), Yang
patent: 5510275 (1996-04-01), Malhi
patent: 5548147 (1996-08-01), Mei

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