Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

1997-03-25

1998-09-15

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 365226, G11C 1604

Patent

active

058089403

ABSTRACT:
A nonvolatile semiconductor memory includes a cell array prepared by arranging erasable and programmable memory cell transistors in rows and columns, word lines arranged in correspondence with the respective rows of the cell array and connected to the control gates of the memory cell transistors, digit lines arranged in correspondence with the respective columns of the cell array and connected to the drains of the memory cell transistors, source lines connected to the sources of the memory cell transistors, and a source power supply circuit for applying a source voltage to the source lines in an erase operation. This memory erases by the source voltage data in the memory cell transistors in the rows and columns of the cell array. The source power supply circuit is a circuit including a first P-channel transistor which sets a current to be supplied to the source lines to a predetermined value in the erase operation in a range wherein the source voltage is lower than a predetermined potential, and a second P-channel transistor which sets the current to be supplied to the source lines so as to decrease faster than the current decreased by the characteristic of the first transistor with an increase in source voltage in a range wherein the source voltage is higher than the predetermined potential.

REFERENCES:
patent: 5491656 (1996-02-01), Sawada
patent: 5586075 (1996-12-01), Miwa

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