Method for fabricating a dynamic random access memory with a ver

Details Method for fabricating a dynamic random access memory with a ver Method for fabricating a dynamic random access memory with a ver

1998-12-04

1999-09-28

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438242, 438253, H01L 218242

Patent

active

059602821

ABSTRACT:
A method for fabricating a DRAM cell with a vertical pass transistor is provided. The method of the invention includes sequentially forming a drain region, a gate structure, a source region, and a capacitor on a semiconductor substrate in a vertical distribution so that an area used by the drain region is the total area used by the DRAM cell on the substrate. In other world, the gate structure, the source region, and the capacitor are formed above the semiconductor substrate without direct contact.

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patent: Re35810 (1998-05-01), Prall
patent: 5106776 (1992-04-01), Shen et al.
patent: 5398200 (1995-03-01), Mazure et al.
patent: 5691221 (1997-11-01), Jun
patent: 5700727 (1997-12-01), Manning
patent: 5792690 (1998-08-01), Sung
patent: 5795804 (1998-08-01), Jenq

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