Method for fabricating a dual-gate dielectric module for memory

Details Method for fabricating a dual-gate dielectric module for memory Method for fabricating a dual-gate dielectric module for memory

1998-05-22

2000-03-14

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438258, 438275, H01L 21336, H01L 218234

Patent

active

060372222

ABSTRACT:
A method of manufacturing a memory device having embedded logic. The memory and logic FETS have two different two gate oxide 20 34 thicknesses. The method integrates (1) a salicide contact process 72 74 (logic devices) and dual gate (N+/P+) logic gate 24A 24B technology with (2) memory device Polycide with Self aligned Contact 80 Technology. The method comprises:

REFERENCES:
patent: 5057449 (1991-10-01), Lowery et al.
patent: 5455444 (1995-10-01), Hsue
patent: 5532181 (1996-07-01), Takebuchi et al.
patent: 5658812 (1997-08-01), Araki
patent: 5668035 (1997-09-01), Fang et al.
patent: 5672521 (1997-09-01), Barsan et al.
patent: 5834352 (1998-11-01), Choi
patent: 5897349 (1999-04-01), Agnello
patent: 5936279 (1999-08-01), Chuang

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