Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-04-27
2000-12-26
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438255, 438396, 438398, H01L 218242
Patent
active
061658405
ABSTRACT:
Disclosed is an improved method for fabricating a DRAM cell capacitor which can prevent over-etching of polysilicon storage node. The method includes the steps of etching a first insulating layer on a semiconductor substrate to form a storage contact hole, filling the storage contact hole with a first conductive material to form a storage contact plug, forming a second insulating layer over the first insulating layer including the storage contact plug, forming a mask over the second insulating layer to define a storage node region, using the mask and etching the second and first insulating layers to form an opening therein to an upper surface of the storage contact plug, and filling the opening with a second conductive material to form a storage node.
REFERENCES:
patent: 5330614 (1994-07-01), Ahn
patent: 5346844 (1994-09-01), Cho et al.
patent: 5792690 (1998-08-01), Sung
patent: 5930623 (1999-07-01), Wu
patent: 5953608 (1999-09-01), Hirota
Choi Chang-Won
Han Min-Seok
Jung Chul
Lee Chang-Hwan
Bowers Charles
Brewster William M.
Samsung Electronics Co,. Ltd.
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