Method for fabricating a DRAM cell capacitor including...

Details Method for fabricating a DRAM cell capacitor including... Method for fabricating a DRAM cell capacitor including...

1999-06-30

2001-05-29

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S397000, C438S399000

Reexamination Certificate

active

06238970

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor manufacturing, and more particularly to a method for fabricating a stacked capacitor.
BACKGROUND OF THE INVENTION
Integrated circuit capacitors are widely used in integrated circuit devices. For example, in Dynamic Random Access Memory (DRAM) devices, integrated circuit capacitors may be used to store charge thereon and thereby store data. As the integration density of DRAM devices continues to increase, it is desirable to maintain sufficiently high storage capacitance while decreasing the area of an integrated circuit substrate that is occupied by each capacitor.
When the integration density of the integrated circuit capacitors is increased, it may become more difficult to align the capacitor lower electrode, also referred to as a storage node, to an underlying contact hole. Moreover, in order to allow relatively high capacitance while decreasing the substrate surface area of the capacitor, the height of the storage node may increase as the area decreases. For example the height of the storage node may increase to one micron or more in a stacked capacitor structure. This may result in a high aspect ratio of the storage node, for example an aspect ratio exceeding 5. This high aspect ratio may make it difficult to pattern a thick conductive layer to form the storage nodes.
A conventional process for stacked capacitor formation is described as follows. An insulating layer is formed over a semiconductor substrate. A contact is opened in the insulating layer to an active region of the semiconductor substrate and conductive material is deposited in the contact opening to form a contact plug. A thick conductive layer is deposited on the insulating layer including the contact plug. Anisotropic etching is carried to etch the thick conductive layer between each contact plug and thereby to form a stacked capacitor. Overetching is conventionally carried out after main etching of the thick conductive layer to obtain etching uniformity and avoid micro bridge between each storage node and the next.
Unfortunately, during anisotropic etching of the storage node, lateral etching may also occur, especially during the overetching process, which may cause the storage node to break. More specifically, as the etching process continues to expose the upper surface of the insulating layer, the exposed layer may be charged positively by etchant. As a result, etchant gas etches the bottom edges of the storage node to cause undercut phenomenon.
SUMMARY OF THE INVENTION
The present invention overcomes or alleviates the above-mentioned and other deficiencies of the prior art by providing a method for fabricating a DRAM cell capacitor which can prevent lateral etching of a capacitor electrode.
It is an object of the invention to provide a method for fabricating a DRAM cell capacitor which can reduce breakage of the capacitor lower electrode during fabrication thereof.
These and other objects are provided, according to the present invention, by forming an anti-reflection coating layer between an oxide layer (wherein a contact is opened) and a polysilicon layer for a storage node. The anti-reflection coating layer is made of material such as SiN or SiON which has relatively lower reflectivity as compared to an underlying oxide layer and also has an etch rate for a predetermined etchant that is intermediate between the insulating layer and the polysilicon layer. Accordingly, the anti-reflection coating layer can allow easier formation of polymer buildup on bottom edges of the lower electrode and thereby prevents lateral etching of the lower electrode at the bottom thereof.
More specifically, stacked lower electrodes are fabricated by forming an insulating layer including an oxide layer on the semiconductor substrate. An anti-reflection coating layer is deposited on the insulating layer. Contacts are opened in the anti-reflection coating layer and the insulating layer. A conductive layer such as polysilicon layer is deposited in the contact openings and on the anti-reflection coating layer to a thickness that determines the height of the lower electrodes. The conductive layer between each contact openings and the next is anisotropically etched to form the lower electrodes.
The anti-reflection coating layer comprises at least one of silicon nitride layer (SiN) and silicon oxynitride (SiON) layer. Anisotropic etching uses a mixture etchant containing hexafluoride (SF
6
), chlorine (Cl
2
) and nitrogen (N
2
) gases. During etching, preferably overetching of the anti-reflection coating layer, a polymer is formed on the bottom edges of the lower electrodes adjacent to the anti-reflection coating layer. The polymer is formed by the reaction between etchant gases and the etched layer. For example, the polymer layer formed comprises SiF
X
N
Y
. Resulting polymer buildup on bottom edges of the lower electrodes protects the bottom edge from etchant gases.
In one aspect of the present invention, contact plug may be formed in the contact opening. In other words, after forming the contact opening, a first conductive material fills the contact opening to form the contact plug. After that, a second conductive layer for the lower electrode is deposited over the anti-reflection coating layer including the contact plug. The second conductive layer is etched to form the lower electrode.


REFERENCES:
patent: 5960293 (1999-09-01), Hong et al.
patent: 6013549 (2000-01-01), Han et al.
patent: 6071787 (2000-06-01), Joo
patent: 6097055 (2000-08-01), Lee et al.

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