Method for fabricating a capacitor

Details Method for fabricating a capacitor Method for fabricating a capacitor

1999-03-12

2001-01-09

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S250000, C438S393000

Reexamination Certificate

active

06171899

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method for fabricating of semiconductor integrated circuits (ICs). and more particularly to a method for fabricating a capacitor.
2. Description of the Related Art
DRAM is a volatile memory, and the way to store digital signals is decided by charge or discharge of the capacitor in the DRAM. Therefore, when the power applied on the DRAM is turned off, the data stored in the memory cell completely disappears. One DRAM cell includes one field effect transistor (FET) and one capacitor. The capacitor is used to store the signals in the DRAM cell. If more charges can be stored in the capacitor, the capacitor has less interference when the data is sensed by the amplifier.
Mixed mode circuits in a semiconductor chip contain capacitors. At present, most capacitors are of the double-polysilicon capacitor (DPC) type as shown in FIG.
1
. As shown in
FIG. 1
, a double-polysilicon capacitor
100
is a capacitor having an upper electrode
104
and a lower electrode
102
, both fabricated from polysilicon material. There is a dielectric layer
106
between the upper electrode
104
and the lower electrode
102
. N-type impurities, for example, can be doped into the polysilicon layer to increase its electrical conductivity. In general, the lower electrode
102
of the double-polysilicon capacitor
100
is connected to a ground terminal while the upper electrode
104
is connected to a negative bias voltage V
bias
. Hence, when the capacitor
100
is being charged, holes within the polysilicon lower electrode
102
migrate to a region on the upper surface of the lower electrode due to the negative bias voltage V
bias
. These holes compensate for the N-type impurities originally doped inside the polysilicon electrode
102
. Consequently, a depletion region
108
is formed on the upper surface of the electrode
102
, thus forming an additional dielectric layer. In other words, an additional dielectric layer is formed over the original dielectric layer
106
, thereby thickening the overall dielectric layer and reducing the charge storage capacity of the capacitor. Furthermore, capacitance of the capacitor is unstable due to some minor fluctuation of the negative bias voltage V
bias
too.
In prior art, metal capacitors, which can prevent a depletion region from forming in a double-poly capacitor, are provided. One of the metal capacitors uses interconnect metal layers as an upper electrode and a lower electrode and uses an inter-metal dielectric layer as the dielectric film for a capacitor. Interconnect metal, inter-metal dielectric and interconnect metal constitute a similar capacitor structure, which is used as a parasitic metal capacitor. However, when the inter-metal dielectric layer is used to isolate two metal layers so that the inter-metal dielectric layer is thick, the dielectric film of a capacitor is thicker and the capacitance is less. The capacitance of the parasitic metal capacitor with a thick inter-metal dielectric layer is thus limited. If the parasitic metal capacitor requires a capacitance the same as that of a conventional capacitor, the parasitic metal capacitor needs a large area because the capacitance increases according to the dielectric area.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer. A photolithography and etching process is performed to remove a part of the second conductive layer. The second metal layer remaining on the inter-layer dielectric layer is used as a wiring line for interconnection. The glue layer remaining on the dielectric film is used as an upper electrode.
In the invention, a first metal layer and a dielectric film are formed on an inter-layer dielectric layer before performing a conventional interconnect process. The first metal layer is defined as a lower electrode of a capacitor. A second metal layer and a glue layer are provided and defined such that a part of the glue layer is used as an upper electrode of the capacitor and a part of the second metal layer is used as a wiring line for interconnection. The dielectric film between the lower electrode and the upper electrode is thin and is of good quality. The capacitance of the capacitor is thus higher than a conventional parasitic metal capacitor.


REFERENCES:
patent: 5624864 (1997-04-01), Arita et al.
patent: 5750419 (1998-05-01), Zafar
patent: 5943583 (1999-08-01), Ochiai
patent: 6022774 (2000-02-01), Kawai et al.

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