Method for fabricating a buried bit line in a DRAM cell

Details Method for fabricating a buried bit line in a DRAM cell Method for fabricating a buried bit line in a DRAM cell

1999-10-21

2001-10-16

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000, C438S430000

Reexamination Certificate

active

06303424

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to a structure and a fabrication method for a dynamic random access memory (DRAM) capacitor. More particularly, the invention relates to a fabrication method for a capacitor over bit-line (COB) DRAM device.
2. Description of the Related Art
In the current information industry, a DRAM device is a very important product. To accompany the advancement and the increased demands on a DRAM device, the DRAM device for an integrated circuit is being designed with increased memory capacity as well as device dimension miniaturization. As a result, a capacitor over bit-line type of DRAM device is being developed.
According to the conventional fabrication method for a COB DRAM device, a transistor is formed in the active region after a shallow trench isolation (STI) structure is formed in the substrate to define the active region of the memory cells. A dielectric layer is further formed to isolate the transistor, followed by forming a bit-line contact in the dielectric layer. A bit line, which is connected to the transistor, is formed on the dielectric layer and in the bit-line contact opening. After another dielectric layer is formed on the bit line, and a node contact is further formed between the two dielectric layers. A capacitor is formed on the second dielectric layer and in the node contact.
According to the above manufacturing process, the steps in forming the bit-line contact, the bit line, the node contact and the capacitor all require the employment of photolithography and etching techniques to define their positions and shapes. Planarization also required after the formation of each of the two dielectric layers to facilitate the subsequent manufacturing process. The conventional approach in forming a COB DRAM device is thus very complicated. Besides, misalignments are likely to occur in each photolithography and etching step. In addition, the formation of the node contact requires the etching of both dielectric layers. The aspect ratio of the node contact is therefore large, which increases the difficulties of the process. As a result, raising the yield for a COB DRAM device becomes very challenging.
SUMMARY OF THE INVENTION
According to the preferred embodiment, the present invention provides a fabrication method for a DRAM device, in which a semiconductor substrate is provided and a pad oxide layer and a nitride layer of a specific pattern are formed on the substrate using the nitride layer as a mask. Etching is conducted on the substrate to form a shallow trench in the substrate and to define an active region. A liner oxide layer is then formed to cover the inner wall of the shallow trench, followed by forming a barrier layer to cover the substrate, including the inner wall of the trench. Thereafter, a first conductive layer is formed to cover the substrate and to fill the shallow trench. A portion of the first conductive layer is then removed, leaving only the first conductive layer in the shallow trench to become a bit line. An insulation layer is then formed to cover the substrate, followed by chemical mechanical polishing the insulation layer until the nitride layer is exposed. A partial etch back is conducted to remove a portion of the conductive layer and the nitride layer. A portion of the pad oxide layer at the peripheral of a side of the shallow trench is further removed to form a bit-line contact, revealing a part of the bit line and extending into the active region.
An elevated feature is formed in the bit-line contact, which is connected to the bit line and covers the area in the active region where the source region is to be formed. The elevated feature includes a second conductive layer, a cap layer, a barrier layer and a spacer. A transistor, including a gate oxide layer, a gate serving as a word line of the memory cells, a gate cap layer, a gate spacer, a source region and a drain region, is formed in the active region. The source region of the transistor extends to the bottom of the elevated feature and is connected to the second conductive layer of the elevated feature. A dielectric layer is then formed to cover the substrate. A node contact is formed in the dielectric layer to expose the drain region of the transistor. A capacitor, connected to the drain region of the transistor, is then formed in the node contact and on the dielectric layer.
According to the above approach, since the bit line is formed in the shallow trench, the space in the integrated circuit is being efficiently used. In addition, only one layer of the dielectric layer is formed, which greatly simplifies the manufacturing process and reduces the number of planarization steps. Furthermore, the dielectric layer, which needs to be etched during the formation of the node contact, is thinner. The aspect ratio of the node contact is thereby lowered, which in turns facilitates the etching process for the formation of the node contact as well as the fabrication of the capacitor.


REFERENCES:
patent: 5283453 (1994-02-01), Rajeevakumar
patent: 5753551 (1998-05-01), Sung
patent: 6048767 (2000-04-01), Terada
patent: 6100155 (2000-08-01), Hu
patent: 8-125144-A (1996-05-01), None

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