Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-03-09
2002-03-26
Clark, Sheila V. (Department: 2815)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S653000
Reexamination Certificate
active
06362099
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a metallization process for manufacturing semiconductor devices. More particularly, the present invention relates to the use of barrier layers having enhanced adhesion to overlying conductive films of copper and other conductive materials.
2. Background
Multilevel metal interconnects having a dimension smaller than 0.20 microns are expected to play a key part in achieving ultra large scale integration (ULSI), which is the next generation of very large scale integration (VLSI). It is also expected that the Damascene process, which involves the deposition of metal into patterned dielectric openings, followed by subsequent chemical-mechanical polishing (CMP) to provide planarization, will also play a key part in achieving such multilevel metal interconnects. As a result, there is a need for a method to reliably deposit metal into patterned dielectric trenches, and to do so in a way that leads to interconnects having desirable properties. The Damascene process is described in Ryu, C., “Microstructure and Reliability of Copper Interconnects,” doctoral thesis, Stanford University (June 1998), which is hereby incorporated by reference.
Aluminum (Al) has been widely used as an interconnect metal because of its good electrical properties. Preferred, known procedures for depositing Al interconnects include chemical vapor deposition (CVD) and physical vapor deposition (PVD). CVD is a preferred procedure for depositing Al into high aspect ratio features of the kind found in Damascene processes, because it leads to good conformal layers of Al, i.e., layers that have a uniform thickness over the substrate surface even when the topography of the surface includes a base and sidewalls requiring step coverage, such as in a trench or contact via. It is known to fabricate Al interconnects by depositing Al by CVD at relatively low temperatures into apertures smaller than 0.5 microns.
However, as device sizes continue to shrink while device densities, chip sizes, and maximum interconnect length increase, the limitations of Al become increasingly apparent. In particular, interconnects having a width smaller than about 0.18 microns are desirable for the next generation of integrated circuits. However, at this dimension, the electromigration of aluminum can cause failures in the interconnect. The resistivity of Al also leads to unacceptably high resistances for long interconnects, which can lead to RC delay, i.e., a delay due to the time required for the energy stored in an interconnect to dissipate. Accordingly, new metals are needed to satisfy the requirements of the next generation of integrated circuits.
Copper (Cu) is currently being investigated as a replacement for aluminum in interconnects. Ryu, which was previously incorporated by reference, provides a review of the current state of the art with respect to copper interconnects. Cu has a bulk resistivity of 1.67 &mgr;&OHgr;-cm, which is approximately 40% less than that of Al (2.66 &mgr;&OHgr;-cm). Also, Cu exhibits resistance to electromigration superior to that of Al under similar circumstances, and lower RC delay. Thus, the lower resistivity of Cu accommodates a higher line density, i.e., a smaller width, while allowing for increased device speed.
Copper interconnects may be deposited by a variety of conventional procedures, such as physical vapor deposition (PVD), electroplating, and electroless plating. Chemical vapor deposition (CVD) is a viable method due to its superior step coverage and selective deposition capability. CVD involves the formation of a reaction product, copper in this case, on a substrate by thermal reaction or decomposition of gaseous compounds, referred to as precursors. Metal-organic CVD (MOCVD), which uses one or more organo-metallic precursors, is preferred for the CVD of copper because they may be used at relatively low temperatures. Preferred organo-metallic precursors include Cu
+2
(hfac)
2
and Cu
+2
(fod)
2
, where hfac is an abbreviation for the hexafluoroacetylacetonate anion, and fod is an abbreviation for heptafluoro dimethyl octanediene.
A preferred process uses the volatile liquid complex copper
+1
(hfac)(tmvs) an a precursor, where tmvs is an abbreviation for trimethylvinylsilane, with argon as a carrier gas. Because this precursor is a liquid under ambient conditions, it can be utilized in standard CVD bubbler precursor delivery systems currently used in semiconductor fabrication. The deposition reaction is believed to proceed on a heated substrate according to the following mechanism, in which (s) denotes interaction with a surface and (g) denotes the gas phase.
(1) 2Cu
+1
(hfac)(tmvs)(g)→2Cu
+1
(hfac)(tmvs)(s)
(2) 2Cu
+1
(hfac)(tmvs)(s)→2Cu
+1
(hfac)(s)+2(tmvs)(g)
(3) 2Cu
+1
hfac(s)→Cu(hfac)(s)+Cu
+2
(hfac)
2
(s)
(4) Cu(hfac)(s)+Cu
+2
(hfac)(s)→Cu(s)+Cu
+2
(hfac)
2
(s)
In step 1, the precursor is adsorbed from the gas phase onto a metallic surface. In step 2, the precursor is dissociated to 2Cu
+1
(hfac) and 2 (tmvs). (tmvs) leaves the surface by desorption. In step 3, Cu(hfac) and Cu
+2
(hfac)
2
are generated by electron exchange between surface Cu
+1
(hfac) species. In step 4, copper metal and volatile Cu
+2
(hfac)
2
are formed by the migration of (hfac) groups. Cu
+2
(hfac)
2
leaves the surface by desorption, leaving copper metal. The overall disproportionation reaction is described by the following equation:
2Cu
+1
(hfac)(tmvs)(
g
)→Cu(
s
)+Cu
+2
(hfac)
2
(
g
)+2(tmvs)(
g
)
Both tmvs and Cu
+2
(hfac)
2
are volatile byproducts of the deposition reaction that are exhausted from the chamber. Cu
+2
(hfac)
2
does not contribute to further deposition because the temperature is much lower than that required for Cu
+2
(hfac)
2
decomposition.
Cu
+1
(hfac)(tmvs) can be used as a precursor to deposit Cu through either a thermal process, or a plasma based process, referred to as plasma enhanced CVD (PECVD). The substrate is preferably held at a temperature between about 100 and 400° C. for PECVD of Cu from Cu
+1
(hfac)(tmvs). The substrate is preferably held at a temperature between about 150 and 220° C., and more preferably at about 170° C., for CVD of Cu from Cu
+1
(hfac)(tmvs) that is not plasma enhanced. Lower temperatures result in a very slow deposition rate, and higher temperatures may adversely affect the resistivity of the resultant interconnect. Thermal CVD is typically preferred over PECVD due to the lower temperatures typically involved with thermal CVD.
However, copper may diffuse into surrounding dielectric or insulating layers, as well as the underlying silicon substrate, and interfere with the desirable properties of those layers. This problem also exists with aluminum, and it is known to use a barrier layer to separate such interconnects from other features. Barrier layers for aluminum interconnects are commonly made from materials that include tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN). It is also known to use a barrier layer to separate copper interconnects from other features. Barrier layers used to separate copper interconnects from other features include those listed above for use with aluminum interconnects. However, while the interaction between these barrier layers and aluminum has been intensively studied, the interaction with Cu may be different. In particular, there is often poor adhesion between barrier layers and the copper interconnects deposited on the barrier layers, which may lead to dewetting and device failures due to high via resistance and poor electromigration reaistance. This problem is particularly pronounced with Cu interconnects deposited by CVD, but may also exist to a lesser extent with Cu deposited by other methods, such as PVD, electroplating, and electroless plating. In addition, an improper selection of a barrier layer may lead to problems with the g
Carl Daniel
Chen Liang
Cong Dennis
Gandikota Srinivas
Ramaswami Sesh
Applied Materials Inc.
Bean Kathi
Church Shirley L.
Clark Sheila V.
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