Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-02-24
2003-04-22
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06553521
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This disclosure relates to semiconductor failure analysis, and more particularly to a method of efficiently classifying failure characteristics on semiconductor memories.
2. Description of the Related Art
Reliability and quality are at the core of the memory chip industry. To insure that these characteristics exist in the large number of chips produced, a method is needed to classify chips quickly and accurately. Classification is used to implement the appropriate corrective procedures to prevent the reoccurrence of failures. Typically, failure analysis has included electrical and visual inspection. When a failure has been identified, it is compared against records of previous failures to categorize the failure and possibly determine its source.
The classification of failure characteristics on semiconductor memories has been preformed by bit-mapping or case-by-case human judgment. The purpose of failure classification is to recognize probable causes of different failures and enable the assignment of an appropriate repair techniques or implementation of adjustments of the manufacturing equipment.
The bit map provides a high degree of detail but is costly and time consuming to produce and store. Likewise, evaluation on a case-by-case basis by skilled engineers is costly and time consuming, and further, it draws the engineers away from other projects. High costs make the current methods economically undesirable in a high-volume manufacturing environment such as in the production of semiconductor memory chips.
Therefore a need exists for an efficient method of analyzing semiconductor failure, which has little effect on throughput and maintains a high degree of accuracy.
SUMMARY OF THE INVENTION
The present invention discloses methods for characterizing semiconductor failures.
The method for characterizing semiconductor failures includes testing a semiconductor chip to determine a fail count, and a fail region count. The fail count is the number of individual failures, and the fail region count is the number of chip regions having at least one failing bit. The method defines the dimensions of semiconductor chip components. Each component may be represented by a characteristic number of bits. The number of bits representing each component relates directly to the number of bits representing each component failure type. The method computes a ratio of the fail count to the fail region count. By comparing component dimensions to the ratio, the method is able to determine a dominant type of component failure on the semiconductor chip. The dominant component failure should have the dimension nearest the ratio.
Component failure types may number two or more. The component failure types may comprise three failure types. The component failure types may include word-lines, bit-lines, and single failures.
A chip region for purposes of this invention can be any distinct group of bits for purposes of testing a semiconductor memory. A chip region may be, for example, the physical location of a block of bits or bits that share a common address characteristic throughout the semiconductor memory.
The step of defining dimensions above may include the steps of: determining the number of individual bits which represent each of the different components; and calculating an average number of bits which represent each component, the averages being determined between components which are proximate in size based on the total number of bits.
The step of defining a ratio may include the step of dividing the fail count by the fail region count to determine the ratio in accordance with the following relationship,
Fail
Count
Fail
Region
Count
=
X
where X is the ratio.
Likewise the step of comparing the dimensions to the ratio may include additional steps. One step may compare the dimensions of the components based on the total number of bits. The method may calculate the average number of bits between components proximate in size, based on the total number of bits. The method may compare the averages to the ratio. By using the averages as threshold values, the method may determine the dominant type of failing component, the dominant type of failing component having a dimension that is the nearest to the ratio as determined from the group of components having dimensions.
Another method for characterizing a semiconductor according to types of failures may include testing a semiconductor chip to determine a fail count, and fail region count. The fail count being the number of individual bit failures, and the fail region count being the number of chip regions having at least one failing bit. The method may define the dimensions of the semiconductor chip components and determine the number of different components. Each component has a characteristic number of bits and the number of bits included in each component relates directly to the number of representative bits included in each of the plurality of component failure types. The method may calculate the average number of bits between each component proximate in size based on the number of bits included in each component. The method may compute the ratio of the fail count to the fail region count. To determine a dominant type of component failure on the semiconductor chip, the method may compare the averages to the ratio. The dominant type of component failure may have the dimension nearest the ratio.
The step of calculating an average number of bits which represent each component may be accomplished in accordance with the following steps:
Calculate (
L+S
)/2
=Y
n−1
.
Where L and S are proximate in size. L is the size of the failure including the larger number of individual bit failures between the pair L and S. S is the size of the failure including the smaller number of individual bit failures between the pair L and S. Y
n−1
is used as a threshold to determine whether the ratio is nearest L. The number of different component types is n. For each subsequent iteration the method may set n=n−1, and L equal to S from the previous calculation of Y
n−
1. The method may calculate additional values of Y until n−1 equals 1.
The step of computing a ratio may be performed in accordance with the following relationship:
Fail
Count
Fail
Region
Count
=
X
where X is the ratio.
The method may compare the averages to the ratio to determine a dominant type of component failure based on the dimensions of each component. For each value of Y
n−1
and its corresponding L and S failure dimensions, the method determines if the ratio is greater then Y
n−1
, if so the dominate failure may be L. If n−1 is equal to 1, the method may determine if the ratio is greater then Y
n−1
, if so the dominant failure may be L, if not the dominant failure dimension may be S.
A method for characterizing semiconductor failures may test for failures to determine a fail count and a fail region count, the fail count being the number of individual failures and the fail region count being a number of regions affected by at least one failure. The method may define dimensions for component failure types for a semiconductor chip, each component represented by a characteristic number of bits. The method may determine the number of different component types. The method may compute a ratio of the fail count to the fail region count, the fail count being the number of individual failures, and the fail region count being the number of chip regions having at least one failing bit.
The method may calculate an average number of bits which represent each dimension, the averages being determined between dimensions which are proximate in size based on a total number of bits. The method may calculate (L+S)/2=Y
n−1
.
Where L is the size of the failure dimension incorporating a larger number of individual bit failures between the pair L and S, S is the size of a failure dimension inc
Giegold Thomas
Rathei Dieter
Wohlfahrt Joerg
Chase Shelly A
De'cady Albert
Infineon Technologies, Richmond L.P.
Slater & Matsil L.L.P.
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