Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-09-18
2003-07-01
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000
Reexamination Certificate
active
06586323
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to create solder bumps for the interconnection of semiconductor devices.
(2) Description of the Prior Art
Semiconductor technology has, ever since its inception, improved semiconductor device performance by reducing device dimensions and, concurrently, increasing device packaging density. In the field of high density interconnect technology, it is necessary for many of the packaging approaches to fabricate a multilayer structure on a substrate in order to connect integrated circuits to one another. To achieve a high wiring and packing density, many integrated circuit chips are physically and electrically connected to a single substrate commonly referred to as a multi-chip module (MCM). Typically, layers of a dielectric such as a polyimide separate metal power and ground planes in the substrate. Embedded in other dielectric layers are metal conductor lines with vias (holes) providing electrical connections between signal lines or to the metal power and ground planes.
The methods that are used to interconnect a semiconductor device to an underlying substrate can be differentiated in methods of wire bonding (device interconnect points are provided around the periphery of the device, a factor that limits the number of input/output connections that can be made to the device), tape automatic bonding (device interconnect points are provided around the periphery of the device, again limiting I/O capability) and C4 or Controlled Collapse Chip Connection methods. The latter method of C4 interconnect offers the advantage of providing high input/output capability since the interconnect bumps can be placed in any location on the chip. The C4 technology offers, in addition to high I/O interconnect capacity, the advantage of short solder bumps (improving the electrical performance of the interconnect) while the process of reflow that is used to connect the solder bumps with the substrate allows the formation of a self-aligned interface between the solder bump and the contact point in the substrate to which the solder bump is connected.
For the formation of solder bumps, two different and well established technologies can be used, that is evaporation and electroplating. Other methods that are used are methods of adhesive applying, stud-bumping methods and the like. These latter methods will not be further discussed at this point.
The method of electroplating follows the processing steps of (over the surface of a substrate wherein a point of electrical contact, typically containing aluminum, has been provided, all steps of processing being centered around this point of electrical contact) depositing a layer of polyimide and etching an opening in this layer of polyimide that aligns with the point of contact, depositing (by vacuum evaporation) a layer of Under Bump Metallurgy (UBM, also referred to as Ball Limiting Metallurgy or BLM) over the layer of poly including the opening created in the layer of poly. A layer of photoresist is deposited over the layer of UBM and patterned, creating an opening in the layer of photoresist that aligns with that part of the layer of UBM that remains in place under the to be created solder bump. Next a layer of metal (typically copper) is electroplated over the layer of photoresist whereby the layer of UBM serves as the common electrode for the electroplating process, the electroplated metal is in contact with the layer of UBM. A layer of solder is next plated over the layer of electroplated metal. The layer of electroplated metal is centered around the opening that has been created in the layer of photoresist as is the layer of plated solder. The photoresist is removed using the solder bump as a mask, the layer of UBM is selectively etched and removed where this layer does not underlie the to be created solder bump in order to electrically isolate the solder bumps from each other. A critical step of the process is performed as a final step whereby a flux is applied to the plated solder and the solder is melted in a reflow furnace under a nitrogen atmosphere, creating a spherically shaped solder bump. The above summarized processing steps of electroplating that are used for the creation of a solder bump can be supplemented by the step of curing or pre-baking of the layer of photoresist after this layer has been deposited over the layer of UBM.
The process of evaporation also starts with a semiconductor surface wherein a metal point of contact has been provided. A layer of passivation is deposited and patterned, creating an opening in the layer of passivation that aligns with the metal point of contact. A layer of UBM is formed over the layer of passivation and inside the opening created in the layer of passivation. The UBM layer may be a composite layer of metal such as chromium followed by copper followed by gold in order to promote (with the chromium) improved adhesion of the UBM layer and to form a diffusion barrier layer or to prevent oxidation (with the gold over the copper). Solder is next selectively plated over the deposited layer of UBM and melted in a solder reflow surface in a hydrogen ambient for solder reflow, in this manner forming the spherically shaped solder bumps.
Some of the problems that have over time been experienced using the various processes are:
electroplating suffers from the problem that the etching of the layer of UBM may affect the solder that has been deposited since this solder is readily attacked by an acid solution; any acid that is used for the etching of the layer of UBM may adversely affect the deposited solder
the previous problem of the solder being affected during the UBM etch can be reduced by the application of a second mask that protects the deposited solder during the UBM etch; this however adds complexity and expense to the process of the formation of solder bumps while the additional mask complicates the processing sequence
the polyimide that is used during the electroplating procedure is difficult to completely remove from the opening that is etched in the layer of poly that aligns with the point of electrical contact; this creates a poorly defined opening in the layer of poly, which in turn results in a low quality contact between the solder bump and the underlying point of electrical contact
the process of electroplating is relatively complex and requires a significant number of processing steps
the process of evaporation is generally more expensive than the process of electroplating, and
the process of evaporation is, for decreased device dimensions, more difficult to control and therefore does not lend itself well to the era of sub-micron devices.
The present invention addresses concerns of a prior art method of forming solder bumps on a semiconductor surface. This prior art method is highlighted in
FIG. 1
, which contains the following sub-components:
10
is a semiconductor surface over which the solder bump is to be created
12
is the metal contact pad, typically containing aluminum, which is to be brought into contact with the solder bump and over which the solder bump therefore is to be created
14
is a patterned layer of Plasma Enhanced silicon nitride, which serves as an etch stop layer for the etch of an overlying layer
16
is a layer of insulation that contains polyamide (a polyamide insulator or PI coating)
18
is a layer of Under Bump Metallurgy (UBM), and
20
is the created solder bump.
The prior art processing sequence for the formation of the solder bump that is shown in
FIG. 1
is as follows:
depositing a layer of PE Si
3
N
4
over the semiconductor surface
10
thereby including the surface of the aluminum pad
12
patterning and etching the deposited layer of PE Si
3
N
4
, creating an opening in the layer of PE Si
3
N
4
that aligns with the aluminum pad
12
applying a coating
16
of polyamide insulator (PI) over the surface of the layer
14
of PE Si
3
N
4
including the exposed surface of the aluminum contact pad
12
patterning and
Chu Cheng-Yu
Fan Fu-Jier
Fan Yang-Tung
Lin Kuo Wei
Lin Shih-Jang
Ackerman Stephen B.
Perkins Pamela
Saile George O.
Taiwan Semiconductor Manufacturing Company
Zarabian Amir
LandOfFree
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