Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-03-24
2000-12-26
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
257296, G11C 2900
Patent
active
061675415
ABSTRACT:
A method of testing a memory device having two arrays of memory cells arranged in rows and columns. Sense amplifiers for respective columns are shared by the arrays, with the sense amplifiers being selectively coupled to the digit lines of respective columns in each array by respective isolation transistors. Cells of the memory array are tested by first writing known data bits to each of the cells. The isolation transistors for the first array are then turned on, and the isolation transistors for the second array are turned off. Predetermined voltages are coupled to the sense amplifiers through the digit lines of the first array by activating a row in the first array. A plurality of rows in the first array are then activated to couple the memory cells in each activated row to respective digit lines. The sense amplifiers are then coupled to respective digit lines in the second array by turning on the isolation transistors for the second array. A plurality of rows in the second array are then activated to couple the memory cells in each activated row to respective digit lines of the second array. The rows in the first and second arrays remain activated for a testing interval of sufficient duration to allow charge to transfer through any inter-cell defects between the cells in the activated rows and cells that are not in an activated row. The cells that are not in an activated row are then read to determine if the data originally written to the cells was altered by charge flowing through inter-cell defects. Inter-cell defects may also be repaired by activating the rows in the first and second arrays in a manner that couples adjacent memory cells to digit lines having different complimentary voltages.
REFERENCES:
patent: H1741 (1998-07-01), Cruts
patent: 4460999 (1984-07-01), Schmidt
patent: 4586178 (1986-04-01), Bosse
patent: 4627053 (1986-12-01), Yamaki et al.
patent: 4639915 (1987-01-01), Bosse
patent: 4736373 (1988-04-01), Schmidt
patent: 4833652 (1989-05-01), Isobe et al.
patent: 5107459 (1992-04-01), Chu et al.
patent: 5159415 (1992-10-01), Min
patent: 5199034 (1993-03-01), Yeo et al.
patent: 5268870 (1993-12-01), Harari
patent: 5291045 (1994-03-01), Atsumi
patent: 5363382 (1994-11-01), Tsukakoshi
patent: 5541862 (1996-07-01), Bright et al.
patent: 5561671 (1996-10-01), Akiyama
patent: 5577050 (1996-11-01), Bair et al.
patent: 5631868 (1997-05-01), Termullo et al.
patent: 5671185 (1997-09-01), Chen et al.
patent: 5694359 (1997-12-01), Park
patent: 5701270 (1997-12-01), Rao
patent: 5748872 (1998-05-01), Norman
patent: 5801412 (1998-09-01), Tobita
patent: 5835409 (1998-11-01), Lambertson
patent: 5866928 (1999-02-01), Seik
patent: 5883899 (1999-03-01), Dahlman et al.
patent: 5898742 (1999-04-01), Van Der Werf
patent: 5917211 (1999-06-01), Murata et al.
patent: 5920575 (1999-07-01), Gregor et al.
patent: 5956275 (1999-09-01), Duesman
patent: 5958075 (1999-09-01), Wendell
patent: 5983366 (1999-11-01), King
patent: 5991907 (1999-11-01), Stroud et al.
patent: 6014762 (2000-01-01), Sanghani et al.
patent: 6026010 (2000-02-01), Ema et al.
patent: 6111947 (1999-12-01), Minne et al.
Lu, et al., (Explosion of Poly-Silicide Links in Laser Programmable Redundancy for VLSI Memory Repair, IEEE, 1989).
Kirihata, et al., (Flexible Test Mode Approach for 256-Mb DRAM, IEEE, 1997).
Takanami, et al., (Reconfigurable Fault Tolerant Binary Tree-Implementation in Two-Dimentional Arrays and Reliabiltiy Analysis, IEEE, 1994).
Chang, et al., (Loop-Based Design and Reconfiguration of Wafer-Scale Linear Arrays with High Harvest Rates, IEEE, 1991).
Al-Assadi, et al., (Modeling of Intra-Cell Defects in CMOS SRAM, IEEE, 1993).
Dufot, et al., (Test Vehicle for a Wafer-Scale Field Programmable Gate Array, IEEE, 1995).
Damon Tim G.
Siek David D.
Cady Albert De
Lamarre Guy
Micro)n Technology, Inc.
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