4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Memory testing

David D. Siek

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6F2 DRAM array with apparatus for stress testing an...

Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate

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6F2 DRAM array with apparatus for stress testing an...

Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate

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DRAM array and computer system

Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate

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Method and apparatus for hiding data path equilibration time

Static information storage and retrieval – Read/write circuit – Precharge
Patent

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Method for detecting or preparing intercell defects in more than

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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Profile ID: LFUS-PAI-P-1168276

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