Method for damascene process

Details Method for damascene process Method for damascene process

2008-04-01

2008-04-01

Zarneke, David A (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S778000, C438S692000, C257SE23011

Reexamination Certificate

active

07351653

ABSTRACT:
Disclosed are methods for carrying out a damascene process in semiconductor fabrication including the steps of: forming an intermetal dielectric film on a semiconductor substrate; patterning the intermetal dielectric film and forming an intermetal dielectric pattern comprising at least two layers of different chemical compositions that includes at least an opening penetrating the intermetal dielectric film; forming a conductive film to fill the opening on the intermetal dielectric pattern; and etching the conductive film by means of a chemical/mechanical polishing operation until exposing an upper face of the intermetal dielectric pattern and the top of the filled opening so as to form a conductive pattern. An etching process is then performed to selectively remove an upper portion of the intermetal dielectric pattern. Because the intermetal dielectric film is variable in chemical composition according to different constituent layers, the upper portion of the intermetal dielectric pattern can be selectively removed by using a chemical etching composition that demonstrates etching selectivity relative to the different layers of the intermetal dielectric film.

REFERENCES:
patent: 6503827 (2003-01-01), Bombardier et al.
patent: 6624063 (2003-09-01), Hasegawa et al.
patent: 2002-134505 (2002-05-01), None
patent: 10-2002-0078368 (2002-10-01), None
patent: 10-2004-0107135 (2004-12-01), None

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