Method for concurrent testing of on-chip circuitry and timing co

Details Method for concurrent testing of on-chip circuitry and timing co Method for concurrent testing of on-chip circuitry and timing co

1997-06-24

2000-07-04

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

326 93, 326 16, 377118, 377119, G06F 1110

Patent

active

060853433

ABSTRACT:
A testing method in which the stages in a multi-stage counter chain are tested sequentially. A counter chain is composed of two or more stages with the carry-out signal from each stage being coupled to the carry-in signal of a subsequent stage. Various circuit modules may be clocked from intermediate stages in the counter chain. In the test mode, the carry-out signal from a given stage is latched once it is asserted. Thereafter, the subsequent stage counts at a higher rate. In this manner, each stage of the chain is run through a complete count, thus verifying the functionality of each stage. Further, the first stage finishes a complete count cycle before the second stage begins counting at a higher rate. A circuit module which is clocked by the output of the first stage is therefore able to complete an operation before any circuit modules clocked by subsequent stages are triggered.

REFERENCES:
patent: 5450555 (1995-09-01), Brown et al.
patent: 5473651 (1995-12-01), Guzinski et al.

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