4. Error detection/correction and fault detection/recovery
  5. Pulse or data error handling
  6. Digital logic testing

Suresh Krishnamoorthy

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Method and system for providing a heuristic approach for...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
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Method for concurrent testing of on-chip circuitry and timing co

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method for determining static flip-flop setup and hold times

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate

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Method for testing circuit design using exhaustive test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Method of determining static flip-flop setup and hold times

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate

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Profile ID: LFUS-PAI-P-1502101

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