Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-05-13
2003-12-09
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S739000, C714S741000
Reexamination Certificate
active
06662327
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the testing of very large scale integration (VLSI) circuits using test patterns (also know as test vectors) that are applied to scan paths within circuits. More particularly, this invention relates to the generation of test patterns for finding random pattern-resistant faults within a VLSI circuit.
BACKGROUND OF THE INVENTION
Most modern digital integrated circuits incorporate a variety of design for testability (DFT) features such as scan path or partial scan to make their testing and diagnosis possible. In test mode, all flip-flops in a full scan design are configured into one or more shift registers called scan paths, with each of the flip flops being a cell of the scan path. This solution provides an excellent controllability and observability of all memory elements in a circuit. Arbitrary test patterns can be applied to the combinational part of the circuit, and its test responses can be observed on the scan cells by a simple shift operation.
The test patterns can be computed and applied in several different ways. One popular approach is to use automatic test pattern generation (ATPG) to compute the test patterns and apply them with a testing device to the circuit under test. The testing device stores the test patterns explicitly, applies them to the circuit under test, and compares the circuit responses to ideal responses to determine if the circuit operates correctly. The ATPG tools available today can generate test patterns with a high degree of fault coverage (i.e., the percentage of possible circuit faults that are detectable) for VLSI circuits. But the storage needed for the large number of test patterns required can easily exceed the testing device's storage capacity.
An alternative to ATPG is Built-In Self Test (BIST), which does not store test patterns. The general state of the art in this area is summarized by V. D. Agrawal, C. K. Kime, and K. K. Saluja, in “A Tutorial on Built-In Self Test, Part 1: Principles,”
IEEE Design and Test of Computers
, March 1993, pp. 73-82, which is incorporated herein by reference. In BIST, hardware within the circuit under test generates test patterns, evaluates test responses, and controls the test application. One popular BIST architecture uses scan paths as a basic DFT technique, Pseudorandom Pattern Generators (PRPG) as sources of test patterns, and multiple input signature registers (MISR) as compactors of test responses. The PRPG uses a linear feedback shift register (LFSR) or a cellular automata (CA) as a source of test patterns capable of generating sequences of millions of test pattern without repetition. The PRPG generates pseudorandom test patterns that are shifted to the circuit under test through scan and boundary scan. Once a test pattern is shifted, the circuit is reconfigured into normal system mode for at least one clock cycle to load the response back to the scan path. At this point the responses are shifted out, while at the same time a new test pattern is shifted in. The test responses obtained from shifting of many scan chains are compacted into a signature. The control circuitry provides the necessary signals which control the test application, determine the number of test patterns applied, the length of the shift operation, etc. The BIST control circuitry on an integrated circuit may be connected to and driven by the IEEE 1149.1 TAP controller. In this case it might be possible to load the initial seed of the PRPG, the number of test patterns to be applied, and read the final signature.
It has been found, however, that many real circuits are resistant to pseudorandom pattern testing. A simple example of such a circuit is a 32-input AND gate. A test for stuck-at-0 fault on the output of this AND gate requires that all 32 inputs assume a value 1. A PRPG which generates test patterns with A 50% probability of a logic 1 on each input must generate on average four billion patterns to detect the fault, a prohibitively large number.
One approach to eliminate random pattern resistance is presented by B. H. Seiss, P. M. Trouborst and M. H. Schulz in “Test Point Insertion for Scan-Based BIST,”
Proceedings of European Test Conference
, 1991, pp.253-262, which is incorporated herein by reference. This approach relies on the insertion of control and observation points into the circuit to increase the controllability and observability of critical areas of the circuit so that faults in these areas can be detected by the application of pseudorandom test patterns. The control points are inserted into the circuit as additional gates or additional inputs to gates. They are disabled in the normal mode, and they do not alter the circuit function (though they may affect circuit delay). In test mode, control points are driven by additional scan cells connected to a PRPG.
This approach addresses the problem of random pattern resistance, but it has some disadvantages. First, there is additional circuit area overhead required for the control points, observation points, and the scan cells to drive them. On average one test point requires ten additional gates. Second, since the control points are driven by the additional scan cells, the points must switch at the same rate as any other inputs to the combinational logic. If BIST is to be applied at-speed, these signals have to be routed with the same timing constraints as any other signals in the circuit logic. Third, due to additional switching on the control points, there is an increased power dissipation during test mode.
Another approach is presented by N. Tamarapalli and J. Rajski in “Constructive Multi-Phase Test Point Insertion for Scan-Based BIST,”
Proceedings of International Test Conference
,” pp. 649-658, 1996, and in U.S. Pat. No. 5,737,340, which are incorporated herein by reference. Multi-phase test point insertion (MTPI) is used to activate the control points in a number of phases. A divide-and-conquer technique partitions the whole test into a number of phases, and a phase decoder circuit activates a subset of control points by applying fixed values for the duration of the phase. The algorithm assigning control points in a given phase targets the faults which remain undetected after the previous phases. The assignments work synergistically to detect the faults while avoiding conflicting assignments, which are activated in different phases. This approach maximizes the fault coverage and minimizes area overhead and power dissipation. It, however, requires that a test point be inserted in every circuit area containing undetected faults. If the area contains very few faults, the returns per insertion increasingly diminish.
For circuits where the insertion of test points is not possible, such as legacy designs, or not desirable due to a possible impact on area performance or design flow, several other techniques have been developed to reduce the amount of test data to store. In weighted random pattern testing, pseudorandom patterns are biased, i.e. the probability of generating logic states 0 and 1 may be different For example, if weighted random patterns are applied to test completely a 32-input AND gate, the optimum probability of value 1 is {fraction (31/32)}, and consequently {fraction (1/32)} for value 0. For those values the average test length of a complete test is approximately 350 patterns, as opposed to four billion for equiprobable patterns. Although the test length is reduced significantly, the method requires storage of weights, i.e., the signal probabilities for each input or scan cell of the circuit. In this example, one set of signal probabilities was used. It has been demonstrated that real circuits require multiple weight sets, in some instances more than a hundred. Each weight set specifies signal probabilities for all inputs of the circuit. It involves up to four bits of data per scan cell. Although this is a significant reduction of data compared to explicit storage of test data, the amount of test data to store is still significant for large circuits. A number of weighted random pattern (
Klarquist & Sparkman, LLP
Lamarre Guy
Tu Christine T.
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