Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-09-19
1999-08-17
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714731, 714744, G01R 3128
Patent
active
059387807
ABSTRACT:
A method for operating automatic test equipment for capturing digital data produced by a semiconductor device under test, whereby the digital data is repetitively sampled to produce a series of sampled data pairs. The digital data and the sampling frequency can be non-coherent. As a result, the digital data can be sampled early relative to some bits and late relative to other bits. The sampled data pairs that are captured while these shifts take place, from early-to-late sampling or from late-to-early sampling, are then assigned to respective groups. A minimum number of bit patterns, corresponding to the sampled digital data, is then derived from contiguous groups of sampled data pairs, and compared with expected bit patterns. The method is especially useful for capturing digital data with drifting frequency.
REFERENCES:
patent: 4373154 (1983-02-01), Balme et al.
patent: 4821297 (1989-04-01), Bergmann et al.
patent: 5598446 (1997-01-01), Van Der Tuijn
Gamache Richard E.
Nguyen Hoa T.
Teradyne, Inc.
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