Method for blocking unknown values in output response of...

Details Method for blocking unknown values in output response of... Method for blocking unknown values in output response of...

2008-02-20

2010-10-19

Ton, David (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000

Reexamination Certificate

active

07818643

ABSTRACT:
A method includes compressing control patterns describing values required at the control signals of blocking logic gates, by linear feedback shift register LFSR reseeding; bypassing blocking logic gates for some groups of scan chains that do not capture unknown values in output response of scan test patterns for testing circuits; and reducing numbers of specified bits in densely specified ones of the control patterns for further reducing the size of a seed of the LFSR.

REFERENCES:
patent: 6557129 (2003-04-01), Rajski et al.
patent: 6789221 (2004-09-01), Hapke
patent: 7197721 (2007-03-01), Patil et al.
patent: 7237162 (2007-06-01), Wohl et al.
patent: 7376873 (2008-05-01), Vranken et al.
patent: 2006/0236186 (2006-10-01), Wang et al.

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