Method for a gate last process

Details Method for a gate last process Method for a gate last process

2011-07-26

2011-07-26

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S510000, C438S692000, C438S740000, C257SE21006, C257SE21058, C257SE21170, C257SE21126, C257SE21127, C257SE21182, C257SE21245, C257SE21267, C257SE21278, C257SE21293, C257SE21304, C257SE21400, C257SE21421, C257SE21585

Reexamination Certificate

active

07985690

ABSTRACT:
A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.

REFERENCES:
patent: 7326645 (2008-02-01), Shim
patent: 7648882 (2010-01-01), Jiang et al.
patent: 2002/0119618 (2002-08-01), Tseng et al.

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