Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2002-01-07
2004-11-16
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S025000, C324S1540PB
Reexamination Certificate
active
06820226
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates generally to testing of designs for integrated circuits, and more particularly to testing for contention among drivers in such designs.
2. Related Art
With modern technology, a tiny integrated circuit having a huge number of transistors can be fabricated in large quantities at a relatively small per unit cost. However, in absolute terms the set up cost for fabrication is not cheap. To achieve low per unit cost integrated circuit chips must be produced in large quantities. Because it is expensive to set up fabrication, and because chips having perhaps millions of transistors are complicated and subject to design glitches, it is common to emulate a chip and extensively test the emulated chip before fabrication.
It is also quite common for chips to interface with one another. In this circumstance, testing is not as simple as just testing a single chip's functionality. Interaction between the chips must also be tested. But even with extensive conventional testing, chips may appear to interact properly and yet have undetected problems.
One commonly undetected problem concerns contention between drivers. This occurs when two drivers that share a transmission line or node both drive at the same time. It is particularly problematic to detect contention because when two drivers contend, one of the drivers typically overpowers the other. This may result in correct logic functioning due to the happenstance of which of the drivers happens to win. However, while correct logic functioning is good, it is not all that matters. Contention that does not impair logic function is still undesirable because it causes unnecessary noise and power dissipation. Moreover, even contention that does not initially impair logic function may lead to incorrect functioning later. For example, logic designs for chips may be somewhat independent of drivers. Thus, in one instance chips may have their logics fabricated with one type of drivers, in which case the chips interact successfully, but in another instance the chips may have a different type of drivers and no longer function properly together. Therefore, a need exists for improvements in testing for contention.
SUMMARY
The foregoing need is addressed in the present invention. In one aspect of the invention, a method for testing includes interposing a tester between first and second logic. The first logic and second logic have respective first and second output drivers. The tester operates in test cycles to detect dynamic contention responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during an immediately succeeding one of the test cycles. Static contention is detected responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during the same one of the test cycles.
In an apparatus form, a tester is for interposing between first and second logic. The first logic and second logic have respective first and second output drivers and the tester is operable in test cycles to periodically test for contention between the drivers. The tester has tester logic, a first tester node for coupling to the first logic driver, and a second tester node for coupling to the second logic driver. A switch of the tester is coupled to the first and second tester nodes, and the tester logic is operatively coupled to the switch to open the switch during a certain interval of the test periods, so that the respective first and second logic may be electrically decoupled from one another. A first test receiver is coupled to the first tester node and to the tester logic for sensing a signal on the first node. Likewise, a second test receiver is coupled to the tester second node and to the tester logic for sensing a signal on the second node. The periodic testing for contention includes signals of the logic output drivers during the certain interval being registered by the tester logic responsive to the respective test receivers.
In another aspect, the tester has a first test source coupled to the first tester node for asserting and de-asserting signals on the first node during one portion of the certain interval responsive to the tester logic, and a second test source coupled to the second tester node for asserting and de-asserting signals on the second node during another portion of the certain interval, also responsive to the tester logic. The test receivers sense the logic driver signals during the certain interval responsive to the test source signals.
Other aspects, as well as advantages and objects of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.
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patent: 5097144 (1992-03-01), Chang et al.
patent: 5548525 (1996-08-01), Albee et al.
patent: 6025708 (2000-02-01), Stickler
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patent: 6631486 (2003-10-01), Komatsu et al.
IBM Technical Disclosure, “AC Chip in Place Test”, NN74111607, Nov., 1974.
Dixon Robert Christopher
Singletary Alan Grant
Carwell Robert M.
England Anthony V. S.
Lamarre Guy J.
Trimmings John P.
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