Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-09-05
2006-09-05
Lamarre, Guy (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S728000
Reexamination Certificate
active
07103816
ABSTRACT:
A method and system for reducing test data volume in the testing of logic products such as integrated circuit chips. Test data loaded by a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “care” bits and “non-care” bits. The care bits target focal faults of interest in the logic circuitry being tested while the non-care bits do not. According to the invention, non-care bits in the test vector data are filled with repetitive background data to provide for a high degree of compressibility of the test vector data. A substantial portion of the care bits may also be set to a repetitive value and the original values later recovered.
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Distler Frank O.
Farnsworth, III Leonard O.
Ferko Andrew
Keller Brion L.
Koenemann Bernd K.
Cadence Design Systems Inc.
Chaudry Mujtaba K.
Lamarre Guy
Orrick Herrington & Sutcliffe LLP
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