Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-30
2002-09-10
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S368000, C257S412000, C257S413000, C257S900000
Reexamination Certificate
active
06448594
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more specifically to a method and system for processing a semiconductor device.
BACKGROUND OF THE INVENTION
Semiconductor manufacturers have increasingly turned to high density Metal Oxide Semiconductor (MOS) arrays in their integrated circuit design schemes. To achieve a high density integrated circuit, features such as metal-oxide semiconductor field-effect transistors (MOSFETs) must be as small as possible. Typically, high density flash memory integrated circuits utilize NAND-type gates as opposed to NOR-type gates since NAND gates have a considerably higher density than NOR gates. Smaller transistors allow more transistors to be placed on a single substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
FIG. 1
illustrates a cross section of two conventional MOSFET cells. The cells
100
and
150
are comprised of gate stacks
102
,
106
on a substrate
108
. To prevent charge leakage, oxide spacers
110
are formed on each side of the gate stacks
102
,
106
. These oxide spacers
110
are separated by a spacer gap
104
and are typically formed using a conventional chemical vapor deposition (CVD) methodology.
As dimensions are reduced in each new generation of integrated circuit, the spacer gaps are smaller (0.32 microns or lower). The subsequent deposition of material over the oxide spacers becomes increasingly problematic as the spacer gap size decreases. To further illustrate this problem, please refer to FIG.
2
.
FIG. 2
illustrates a semiconductor device wherein material
160
(i.e. Tetraethyl Orthosilicate) deposited over the gate stacks
102
,
106
is unable to get in the smaller spacer. gap
104
′ due to the rectangular shape of the oxide spacers
110
. A void
170
is thereby created. These voids are the result of the inability of the material
160
to get around the edges
112
of the rectangular shaped oxide spacers
110
. Voids create weaknesses in the oxide spacers
110
thereby reducing the reliability of the device. Consequently, by utilizing conventional techniques, material that is subsequently deposited over the oxide spacers
110
cannot adequately fill the spacer gaps.
Accordingly, what is needed is a method for eliminating voids in the spacer gaps of semiconductor devices. The present invention addresses such a need.
SUMMARY OF THE INVENTION
In a first aspect of the present invention, a semiconductor device is disclosed. The semiconductor device comprises at least two gate stacks, each gate stack having two sides and oxide spacers on each of the two sides of each of the at least two gate stacks, wherein at least one of the oxide spacers is triangular shaped.
In a second aspect of the present invention, a method and system for processing a semiconductor device is disclosed. The method and system for processing a semiconductor comprise forming at least two gate stacks over a semiconductor substrate, depositing an oxide layer over the at least two gate stacks, and etching the oxide layer to form at least one oxide spacer in between the at least two gate stacks, wherein the at least one oxide spacer is triangular shape.
Through the use the present invention, the voids that are created in the semiconductor device during conventional semiconductor processing are eliminated. This is accomplished by creating oxide spacers having a triangular shape when etching the oxide layer to form the oxide spacer. By creating a triangular shaped oxide spacer, subsequent layers of material can be deposited over the oxide spacer without creating voids in the semiconductor device. Accordingly, as a result of the use of the present invention, the oxide spacers are strengthened, which increases the reliability of the semiconductor device.
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patent: 5950104 (1999-09-01), Linliu
patent: 5962897 (1999-10-01), Takemura et al.
patent: 6057581 (2000-05-01), Doan
patent: 6133074 (2000-10-01), Ishiwa et al.
patent: 6218251 (2001-04-01), Kadosh et al.
Wolf, S., “Silicon Processing for the VLSI Era”, vol. 3—“The Submicron MOSFET”, Lattice Press, Sunset Beach, California (1995), Chapter 9, pp. 634-636.
Chan Maria C.
Chang Mark S.
Fang Hao
Ko King Wai Kelwin
You Lu
Advanced Micro Devices , Inc.
Flynn Nathan J.
Mondt Johannes P.
Sawyer Law Group LLP
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