Method and system for performing built-in-self-test routines...

Details Method and system for performing built-in-self-test routines... Method and system for performing built-in-self-test routines...

2007-06-29

2009-02-17

Kerveros, James C (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07493541

ABSTRACT:
A test system includes a built-in self-test (BIST) circuit and a stress applicator for use in analyzing a memory array. The stress applicator applies a selective set of stress factors to the memory array, such as temperature and voltage conditions. The BIST circuit executes a test routine on the memory array to detect the presence of any faulty memory address locations that may arise under the prevailing stress condition. A full testing cycle involves iterative repetition of the functions performed by the stress applicator and BIST circuit, with variations in the stress factors across the testing iterations. An accumulator cumulatively stores the fault information generated by the BIST circuit during each testing iteration. Following completion of the testing cycle, a repair operation is performed by a built-in self-repair (BISR) circuit to remap the faulty memory address locations indicated by the accumulator to redundant memory address locations.

REFERENCES:
patent: 5375091 (1994-12-01), Berry et al.
patent: 5831989 (1998-11-01), Fujisaki
patent: 6085334 (2000-07-01), Giles et al.
patent: 6327680 (2001-12-01), Gervais et al.
patent: 6574763 (2003-06-01), Bertin et al.

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