Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-25
2004-09-21
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
59, 59
Reexamination Certificate
active
06794252
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention related generally to semiconductor manufacturing and more particularly to a method and system for forming dual work function gate electrodes in a semiconductor device.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Integrated circuits are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, integrated circuits are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Typically, as the fabrication of integrated circuits has improved, the thickness of many layers formed in the integrated circuits has been reduced. For example, in the relatively recent past, conventional transistor gate dielectric layers had a thickness on the order of 100 Å. However, more recently, these layers have been formed with a thickness on the order of 20 Å. This trend toward thinner gate dielectric layers may continue, as thinner layers reduce device size and facilitate improved device performance.
However, disadvantages associated with thinner gate dielectrics include the proportionally increased dielectric effect corresponding to a depletion region at the interface between the gate dielectric and a polysilicon gate layer formed over the gate dielectric. Typically, the depletion region provides the electrical equivalent of an insulator approximately 3 Å thick.
Thus, continuing with the preceding example, for a 100 Å thick gate dielectric, a depletion region of 3 Å effectively increases the overall insulation between the gate and the underlying transistor channel from 100 Å to 103 Å. As such, for thicker gate dielectrics, the effect of the depletion region may be considered to have a negligible impact on the gate dielectric. In contrast however, for a 20 Å thick gate dielectric, a depletion region of 3 Å increases the gate insulator to 23 Å, which is an increase of approximately 15 percent. This may result in a significant reduction in the benefits otherwise provided by the thinner gate dielectric.
One approach to avoiding the depletion region effect of polysilicon transistor gates uses metal as an alternative material for the transistor gate because metal does not present a considerable depletion region, if any. Problems with this approach include the fact that each metal has a single corresponding work function; however, the desired work function values for different transistor types are not the same. Thus, metal gates result in problems with CMOS circuits, which include both PMOS and NMOS transistors. Specifically, because a metal gate provides only a single work function, two different work functions are not provided for the PMOS and NMOS devices with one metal.
A more recent approach to avoiding the depletion region effect of polysilicon transistor gates provides for the formation of a set of transistor gates where one gate is formed from a metal and the other gate is formed from a corresponding metal silicide. Each transistor gate may then have a different work function. However, with this approach, the work functions provided by the metal and its corresponding metal silicide may not be adjustable.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and system for forming dual work function gate electrodes in a semiconductor device are provided that substantially eliminate or reduce disadvantages and problems associated with previously developed systems and methods. In particular, a metal or other suitable element and its corresponding silicon-germanium metal compound are used to provide two different work functions for two different types of gate electrodes, with one of the work functions adjustable by varying the silicon-to-germanium ratio.
In one embodiment of the present invention, a method is provided for forming dual work function gate electrodes in a semiconductor device. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.
In another embodiment of the present invention, an integrated circuit comprising dual work function gate electrodes is provided. The integrated circuit includes a first gate electrode and a second gate electrode. The first gate electrode comprises a metal layer and has a first work function. The second gate electrode comprises a silicon-germanium metal compound layer and has a second work function. The silicon-germanium metal compound layer is formed from a silicon-germanium layer and the metal layer.
Technical advantages of the present invention include providing an improved method for forming dual work function gate electrodes in a semiconductor device. In a particular embodiment, a metal or other suitable element and its corresponding silicon-germanium metal compound are used for two different types of gate electrodes. As a result, one of the work functions is adjustable based on the silicon-to-germanium ratio in the silicon-germanium metal compound. Accordingly, two different work functions, one of which may be fine-tuned to desired a value, are provided for the two different types of gate electrodes.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
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patent: 6235568 (2001-05-01), Murthy et al.
patent: 6383879 (2002-05-01), Kizilyalli et al.
patent: 6518106 (2003-02-01), Ngai et al.
Rotondaro Antonio L. P.
Visokay Mark R.
Brady III W. James
Chaudhari Chandra
McLarty Peter K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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