Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-11-21
2001-12-18
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185030, C365S185290
Reexamination Certificate
active
06331951
ABSTRACT:
FIELD OF INVENTION
The present invention relates generally to memory systems and in particular to systems and methods for verifying erasure of sectors of bits in electronic memory devices.
BACKGROUND OF THE INVENTION
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 300K write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, which can be erased in lace, flash memory is less expensive and more dense. This new category of EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each cell. In such single bit memory architectures, each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a word line associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bit line. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a single column is connected to the same bit line. In addition, each flash cell has its stacked gate terminal coupled to a different word line, while all the flash cells in the array have their source terminals coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Such a single bit stacked gate flash memory cell is programmed by applying a relatively high voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source. A resulting high electric field across the tunnel oxide leads to a phenomena called “Fowler-Nordheim” tunneling. During this process, electrons in the core cell channel region tunnel through the gate oxide into the floating gate and become trapped in the floating gate since the floating gate is surrounded by the interpoly dielectric and the tunnel oxide. As a result of the trapped electrons, the threshold voltage of the cell increases. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed.
In order to erase a typical single bit stacked gate flash memory cell, a relatively high voltage is applied to the source, and the control gate is held at a negative potential, while the drain is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow toward and cluster at the portion of the floating gate overlying the source region and are extracted from the floating gate and into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased.
In conventional single bit flash memory devices, an erase verification is performed to determine whether each cell in a block or set of such cells has been properly erased. Current single bit erase verification methodologies provide for verification of bit or cell erasure, and application of supplemental erase pulses to individual cells which fail the initial verification. Thereafter, the erased status of the cell is again verified, and the process continues until the cell or bit is successfully erased or the cell is marked as unusable.
Recently, dual bit flash memory cells have been introduced, which allow the storage of two bits of information in a single memory cell. The conventional erase verification methods employed with single bit stacked gate architectures may be applied in certain circumstances to such dual bit devices. However, there is a need for new and improved erase verification methods and systems, which ensure proper erasure of data bits in a dual bit memory architecture, and which account for the structural characteristics thereof
SUMMARY OF THE INVENTION
A system and methodology are provided which overcome or minimize the problems and shortcomings of conventional memory cell erasure verification schemes and systems. The invention includes methods and systems for verifying erasure of one or more dual bit cells in a memory device, such as a flash memory. The invention allows for efficient and thorough erasure verification, which minimizes data retention and over-erase issues particular to the dual bit cell architecture. The invention provides significant advantages when employed in association with dual bit memory cells wherein only one bit thereof is actively used for data storage. However, it will be recognized that the invention finds utility in association with dual bit memory cell architectures generally, and that the invention is thus not limited to any particular dual bit cell usage implementation or configuration.
In accordance with one aspect of the invention, there is provided a method of verifying erasure of a dual bit memory cell, which includes a first bit and a second bit. The erasure verification method comprises the steps of performing a determination of whether a first bit in the dual bit memory cell is properly erased, performing a first verification of whether a second bit in the dual bit memory cell is properly erased if the first bit is properly erased, and determining that the dual bit memory cell is properly erased if the first bit is properly erased and if the second bit is properly erased according to the first verification.
Verification of proper erasure of both bits in a dual bit memory cell configuration according to the inventive method ensures that data retention and/or bit over-erase problems associated with one of the bits in the cell do not adversely affect the operation (e.g., proper erasure, read/write functionality) of the other bit. In this manner, the invention provides significant performance advantages over conventional methods typically utilized in erasure of single bit (e.g., stacked gate) memory cell types. The method may further comprise repeating the method for another dual bit memory cell, whereby a cell by cell erasure verification may be accomplished, for example, in association with a chip erase or sector erase operation. The verifications of bit erasure may be performed through the application of a voltage to the memory cell being verified along with a measurement of a current in the cell.
In addition to the above, the method may also include erasing the first bit if the first bit is not properly erased, and performing a second verification of whether the second bit is properly erased after erasing the first bit, where erasing the first bit comprises applying a voltage to the cell. In this fashion, the method attempts to re-eras
Bautista, Jr. Edward V.
Chen Pau-Ling
Hamilton Darlene G.
Lee Weng Fook
Wong Keith H.
Advanced Micro Devices , Inc.
Eschweiler & Associates LLC
Mai Son
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