Method and structure to reduce CMOS inter-well leakage

Details Method and structure to reduce CMOS inter-well leakage Method and structure to reduce CMOS inter-well leakage

2005-09-20

2005-09-20

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06946710

ABSTRACT:
A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and align to a sidewall of the trench; filling the trench with an insulator; and forming an N-well (or a P-well) in the substrate adjacent to and in contact with an opposite sidewall of the trench, the N-well (or the P-well) extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench. The leakage control implant is self-aligned to the trench sidewalls.

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